i.MX ProcessorsのトピックRe: SDIO/MMC v2/3 Host Throughput

SDIO/MMC v2/3 Host Throughput

lyfsci — Tue, 25 Nov 2014 10:06:47 GMT

Hi Experts,

What is the maximum effective throughput that could be achieved in the SD/MNC host controller for the various IMX series of processors (IMX 3/5/6) ?

Is there any test suite for EVK or respective factory profiled value for the various platforms along with its associated scenarios ?

Re: SDIO/MMC v2/3 Host Throughput

art — Fri, 28 Nov 2014 02:46:21 GMT

The SD/MMC controller cores of the i.MX3x and i.MX5x series processors are pretty similar. They support the SD/SDIO v.2.0 specification and MMC v.4.2 specification. The Reference Manual documents for these processor series specify the following communication parameters of the SD/MMC controller cores.

— Card bus clock frequency up to 52 MHz

— Up to 416 Mbits/s of data transfer for MMC cards in 8-bit mode

— Up to 200 Mbits/s of data transfer for SD/SDIO cards in 4-bit mode

The SD/MMC controller cores of the i.MX6x series processors support the SD/SDIO v.3.0 specification and MMC v.4.41 specification. The Reference Manual documents for these processor series specify the following communication parameters of the SD/MMC controller cores.

Bus clock frequencies supported are:

- MMC full speed mode (up to 20 MHz)

- MMC high speed mode (up to 52 MHz)

- MMC DDR mode (52MHz both edges)

- SD/SDIO full speed mode (up to 25 MHz)

- SD/SDIO high speed mode (up to 50 MHz)

- SD/SDIO UHS-I mode(up to 208Mhz in SDR mode, up to 50Mhz in DDR mode)

The corresponding data rates are:

- Up to 832 Mbits/s of data transfer for SD/SDIO cards using 4 parallel data lines in SDR(Single Data Rate) mode

- Up to 400 Mbits/s of data transfer for SD/SDIO card using 4 parallel data lines in DDR(Dual Data Rate) mode

- Up to 832 Mbits/s of data transfer for SDXC cards using 4 parallel data lines in SDR(Single Data Rate) mode

- Up to 400 Mbits/s of data transfer for SDXC card using 4 parallel data lines in DDR(Dual Data Rate) mode

- Up to 416 Mbits/s of data transfer for MMC cards using 8 parallel data lines in SDR(Single Data Rate) mode

- Up to 832 Mbits/s of data transfer for MMC cards using 8 parallel data lines in DDR(Dual Data Rate) mode

There are no dedicated test cases for SD/MMC controller cores speed test, since the real data throughput depends on many factors, such as speed of device connected, software overhead etc.

Have a great day,
Artur

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Re: SDIO/MMC v2/3 Host Throughput

lyfsci — Sat, 29 Nov 2014 07:58:40 GMT

Hi Artur,

Thanks for the response.

The above mentioned items seems to be the ideal throughput value whereas I look for the actual throughput achieved beyond the signaling constraints in the SoC.

Re: SDIO/MMC v2/3 Host Throughput

dfasano — Wed, 31 May 2023 20:03:27 GMT

I am going to use the Variscite DART6UL board for a project. It has the NXP i.MX 6 Ultralite ARM Cortex-A7 processor. I need to transfer data at 20MB/sec to a SD card.

Does anyone know if that kind of throughput rate is possible with the SD driver running and managing the file structure and writing operation to the SD FLASH memory?

I am concerned about the overhead the driver will impose on the overall data-rate.

Also, am I correct in assuming the data can be moved under DMA from a parallel input port to the SD bus?

Thanks in advance,

Dan