topic Re: Re: MMPF0100F3AEP Power up issue in i.MX Processors

MMPF0100F3AEP Power up issue

muthunagarajan — Thu, 30 Oct 2014 15:52:19 GMT

I'm seeing a power up issue with the MMPF0100F3AEP PMIC where on ramping Vin > UVDET the SNVS voltage will only power-up to ~0.83V and stay there. This causes all the regulators in the PMIC to not start-up.

In our application we turn ON and OFF the Vin input to the PMIC and I ensured that the Vin voltage discharges to well below the falling UVDET threshold before powering it back again.

The LICELL input is floating other than the recommended bypass capacitor. Any idea why SNVS won't power up to its normal voltage of 3V?

Looking at the State diagram, it looks like the PMIC goes to the Coin cell state when Vin falls below UVDET, and the next time I apply power Vin > UVDET it is

going into OFF state. How do I get it to transition to the ON state?

Thanks

Muthu

Re: MMPF0100F3AEP Power up issue

igorpadykov — Thu, 30 Oct 2014 16:53:49 GMT

Hi Muthu

for PMIC turn on only Vin > UVDET is not sufficient, from

sect.6.4.2.1Turn On Events MMPF0100 :

•If PWRON_CFG = 0, the PWRON signal is high and VIN > UVDET, the PMIC will turn on

•If PWRON_CFG = 1, VIN > UVDET and PWRON transitions from high to low, the PMIC will turn on

Since it is not turned on then only source for SNVS voltage is LICELL, with

LICELL input is floating, SNVS voltage can not be produced.

In general LICELL bypass capacitor is very important, since it powers PMIC core

during VIN power glitches.

Best regards

igor

Re: MMPF0100F3AEP Power up issue

muthunagarajan — Thu, 30 Oct 2014 17:04:23 GMT

Hi Igor,

Thanks for responding.

From what I understand, the PWRON pin has an internal pull-up to SNVS voltage on the MMPF0100F3AEP (which is the PF0100A version).

So when I ramp Vin > UVDET, I expect SNVS to power up to 3V causing PWRON to be high to enable the PMIC to turn ON. But for some

reason the SNVS voltage is stuck at 0.83V. Any idea why the SNVS voltage not power up correctly?

It looks like the PWRON_CFG register is set to 0 for the factory programmed PMIC's. We read this register value using the Freescale prog. kit for the MMPF0100F3AEP PMIC.

Also, in my design I have VDDOTP pin connected to ground, its not clear what this connection should be for a factory programmed PMIC.

I'm mentioning this as an additional data point, in case this somehow has an effect on the problem I'm having.

Thanks

Muthu

Re: MMPF0100F3AEP Power up issue

igorpadykov — Fri, 31 Oct 2014 03:10:23 GMT

Hi Muthu

regarding "PWRON pin has an internal pull-up to SNVS" :

since yoi have not LICELL (as you mentioned LICELL input is floating)

SNVS is not powered. Please attach LICELL.

~igor

Re: MMPF0100F3AEP Power up issue

muthunagarajan — Fri, 31 Oct 2014 03:31:28 GMT

Do I need LICELL or Vin to be at a valid voltage level always for a proper power-up?

In my current board LICELL is floating and the board will sometimes power-up correctly but most times it won't.

May be I mis-understood how LICELL is supposed to be hooked up, but I followed AN4717 - Recommended pin connections.

Can you explain to me when can LICELL be left floating with just a bypass cap as stated in AN4717?

In my design Vin is 3.6V, can I tie LICELL to Vin? It shouldn't matter per the datasheet because SNVS is derived from the best of the two supplies Vin and LICELL.

Thanks

Muthu

Re: MMPF0100F3AEP Power up issue

igorpadykov — Fri, 31 Oct 2014 07:15:39 GMT

Hi Muthu

MMPF0100 sect.6.4.7.1 Coin Cell Battery Backup :

systems not utilizing a coin cell, connect the LICELL pin to any system voltage

between 1.8 and 3.0 V.

A small capacitor should be placed from LICELL to ground under all circumstances.

Table 4. PF0100 Pin Definitions:

LICELL Coin cell supply input/output IO 3.6 V Max Rating

~igor

Re: MMPF0100F3AEP Power up issue

muthunagarajan — Fri, 31 Oct 2014 16:24:05 GMT

I will try that.

Just to clarify further, is there a case where the LICELL voltage doesn't have to be valid, i.e. no coin cell or other system voltage connected to it

where the PMIC will power up correctly?

Thanks

Muthu

Re: Re: MMPF0100F3AEP Power up issue

igorpadykov — Sat, 01 Nov 2014 15:16:56 GMT

Hi Muthu

please refer to attached picture,

"LICELL pin connection for systems not using a coin cell" option.

Regarding your question, I think there is no simple answer and it may

depend on many factors.

~igor

Re: MMPF0100F3AEP Power up issue

muthunagarajan — Sat, 01 Nov 2014 18:37:58 GMT

This is conflicting with the Revision history in the MMPF0100 datasheet, can you confirm which one is the latest recommendation?

6.0 8/2013 • Removed LICELL connection to VIN on PF0100A

Thanks

Muthu

Re: MMPF0100F3AEP Power up issue

igorpadykov — Sun, 02 Nov 2014 00:26:17 GMT

Could you please create SR ticket with attached

schematic, for elevating this to Analog Experts team ?

Best regards

igor

Re: MMPF0100F3AEP Power up issue

igorpadykov — Tue, 04 Nov 2014 11:13:57 GMT

Hi Muthu

I can confirm that below indeed is the latest recommendation:

6.0 8/2013 • Removed LICELL connection to VIN on PF0100A

However this is general product description, not taking into account i.MX6

specifics. From my point of view there may be problem with i.MX6

connection, since at very first power-up it significantly overloads MMPF0100 VSNVS.

Max. MMPF0100 VSNVS current is 0.4mA.

From footnote 2 to Table 8 "Maximum Supply Currents" IMX6DQCEC :

"During initial power on, VDD_SNVS_IN can draw up to 1 mA.."

From Table 2-6 "Power and decouple recommendations" IMX6DQ6SDLHDG ,

"2 Do not overload coin cell backup power rail VDD_SNVS_IN" :

"When VDD_SNVS_IN > VDD_HIGH_IN, VDD_SNVS_IN supplies current

to SNVS, and some current flows into VDD_HIGH_IN.."

~igor

Re: MMPF0100F3AEP Power up issue

muthunagarajan — Tue, 04 Nov 2014 14:44:49 GMT

Hi Igor,

The response on the SR I submitted said the same thing that just a bypass cap on the LICELL is sufficient.

But as you mentioned this may be specific to iMX6. If it helps any I'm using the MCIMX6L2EVN10AB version of the iMX6SL.

I'm using the F3 option for the PMIC which has VDD_HIGH_IN power up first right after SNVS. Per the discussion in

I cannot find the PF0100F3 PMIC, is it really necessary for the iMX6SL?

this high current draw from SNVS should not occur, did I interpret that right?

Thanks

Muthu

Re: MMPF0100F3AEP Power up issue

igorpadykov — Tue, 04 Nov 2014 15:46:46 GMT

Hi Muthu

unfortunately behaviour with high current draw from SNVS at first power up

moment happens for all processors. Option F3 (PF0100F3 PMIC) alleviates problem

moving SW2 (supplying VDD_HIGH, it supplies i.MX6 VSNVS through D24 on i.MXSL EVK

schematic spf-27452) at first step of power-up sequence, but until SW2 will turn on,

high current draw from i.MX6 SNVS still may occur.

Best regards

igor