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<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
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    <title>i.MX ProcessorsのトピックRe: internal boot from uSHC2</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/internal-boot-from-uSHC2/m-p/366693#M52047</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;one can connect jtag debugger and check&lt;/P&gt;&lt;P&gt;SRC_SBMR1,2 registers, they should have&lt;/P&gt;&lt;P&gt;correct boot settings, which set by boot pins.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 11 Feb 2015 15:17:10 GMT</pubDate>
    <dc:creator>igorpadykov</dc:creator>
    <dc:date>2015-02-11T15:17:10Z</dc:date>
    <item>
      <title>internal boot from uSHC2</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/internal-boot-from-uSHC2/m-p/366690#M52044</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;We are using i.MX6 Solo processor. For that we are using boot mode 10 (internal boot mode) and done GPIO setting for boot from uSHC--2 (microSD card). But it is not booting from it. I have checked the clock and command lines, but I have not seen any activity there.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;In boot mode 00,&amp;nbsp; because of manufacturing mode it is booting from uSHC--2 (microSD card).&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I have checked all the GPIO settings. For reference I have attaché d the GPIO settings.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;With regards&lt;/P&gt;&lt;P&gt;LK&lt;/P&gt;&lt;P&gt;&lt;BR /&gt; &lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 11 Feb 2015 13:22:07 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/internal-boot-from-uSHC2/m-p/366690#M52044</guid>
      <dc:creator>lk22</dc:creator>
      <dc:date>2015-02-11T13:22:07Z</dc:date>
    </item>
    <item>
      <title>Re: internal boot from uSHC2</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/internal-boot-from-uSHC2/m-p/366691#M52045</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Lalit&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;does second POR (without power-off board) help ?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;&lt;P&gt;igor&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 11 Feb 2015 13:46:45 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/internal-boot-from-uSHC2/m-p/366691#M52045</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2015-02-11T13:46:45Z</dc:date>
    </item>
    <item>
      <title>Re: internal boot from uSHC2</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/internal-boot-from-uSHC2/m-p/366692#M52046</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;No. I have tried many resets (without power off) after that.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 11 Feb 2015 14:18:36 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/internal-boot-from-uSHC2/m-p/366692#M52046</guid>
      <dc:creator>lk22</dc:creator>
      <dc:date>2015-02-11T14:18:36Z</dc:date>
    </item>
    <item>
      <title>Re: internal boot from uSHC2</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/internal-boot-from-uSHC2/m-p/366693#M52047</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;one can connect jtag debugger and check&lt;/P&gt;&lt;P&gt;SRC_SBMR1,2 registers, they should have&lt;/P&gt;&lt;P&gt;correct boot settings, which set by boot pins.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 11 Feb 2015 15:17:10 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/internal-boot-from-uSHC2/m-p/366693#M52047</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2015-02-11T15:17:10Z</dc:date>
    </item>
    <item>
      <title>Re: internal boot from uSHC2</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/internal-boot-from-uSHC2/m-p/366694#M52048</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Yes,&amp;nbsp; SRC_SBMR1,2 registers have correct boot settings.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 11 Feb 2015 15:58:37 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/internal-boot-from-uSHC2/m-p/366694#M52048</guid>
      <dc:creator>lk22</dc:creator>
      <dc:date>2015-02-11T15:58:37Z</dc:date>
    </item>
    <item>
      <title>Re: internal boot from uSHC2</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/internal-boot-from-uSHC2/m-p/366695#M52049</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;had you checked SD2 signals by ocilloscope&lt;/P&gt;&lt;P&gt;during power-up, have you valid signal on CD,&lt;/P&gt;&lt;P&gt;as shows Table 8-18 &lt;A href="http://cache.freescale.com/files/32bit/doc/ref_manual/IMX6SDLRM.pdf?fasp=1&amp;amp;WT_TYPE=Reference%20Manuals&amp;amp;WT_VENDOR=FREESCALE&amp;amp;WT_FILE_FORMAT=pdf&amp;amp;WT_ASSET=Documentation&amp;amp;fileExt=.pdf"&gt;IMX6SDLRM&lt;/A&gt;&amp;nbsp;&amp;nbsp; ?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 11 Feb 2015 16:09:14 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/internal-boot-from-uSHC2/m-p/366695#M52049</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2015-02-11T16:09:14Z</dc:date>
    </item>
    <item>
      <title>Re: internal boot from uSHC2</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/internal-boot-from-uSHC2/m-p/366696#M52050</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Yes. I have checked all gpio settings. Also checked cmd and clock lines with boot mode 00 and 10. In boot mode 10 there is no signal,while in boot mode 00 i was able to get the clock in oscilloscope.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;CD is low then only it is booting from sd-2 in boot mode 00.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 11 Feb 2015 17:29:38 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/internal-boot-from-uSHC2/m-p/366696#M52050</guid>
      <dc:creator>lk22</dc:creator>
      <dc:date>2015-02-11T17:29:38Z</dc:date>
    </item>
    <item>
      <title>Re: internal boot from uSHC2</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/internal-boot-from-uSHC2/m-p/366697#M52051</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;why CD level different in two cases ?&lt;/P&gt;&lt;P&gt;It is output from SD card and should be correct (card present)&lt;/P&gt;&lt;P&gt;in both cases.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 12 Feb 2015 01:11:15 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/internal-boot-from-uSHC2/m-p/366697#M52051</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2015-02-12T01:11:15Z</dc:date>
    </item>
    <item>
      <title>Re: internal boot from uSHC2</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/internal-boot-from-uSHC2/m-p/366698#M52052</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;It is same in both cases, not different.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 12 Feb 2015 01:21:51 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/internal-boot-from-uSHC2/m-p/366698#M52052</guid>
      <dc:creator>lk22</dc:creator>
      <dc:date>2015-02-12T01:21:51Z</dc:date>
    </item>
    <item>
      <title>Re: internal boot from uSHC2</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/internal-boot-from-uSHC2/m-p/366699#M52053</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;what reference design is based your board - is it Freescale&lt;/P&gt;&lt;P&gt;reference board ? Also is pmic used, if yes what its full marking ?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 12 Feb 2015 01:44:51 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/internal-boot-from-uSHC2/m-p/366699#M52053</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2015-02-12T01:44:51Z</dc:date>
    </item>
    <item>
      <title>Re: internal boot from uSHC2</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/internal-boot-from-uSHC2/m-p/366700#M52054</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Yes, I had referred Freescale SABRE-AI_DualLite_CPUcard&lt;/P&gt;&lt;P&gt;PMIC marking is&lt;/P&gt;&lt;P&gt;MMPF0100&lt;/P&gt;&lt;P&gt;F2EP&lt;/P&gt;&lt;P&gt;DKHYDC&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;With regards&lt;/P&gt;&lt;P&gt;LK&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 12 Feb 2015 04:48:15 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/internal-boot-from-uSHC2/m-p/366700#M52054</guid>
      <dc:creator>lk22</dc:creator>
      <dc:date>2015-02-12T04:48:15Z</dc:date>
    </item>
    <item>
      <title>Re: internal boot from uSHC2</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/internal-boot-from-uSHC2/m-p/366701#M52055</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;please check by oscilloscope voltages (_ARM_CAP,SOC_CAP,HIGH_CAP)&lt;/P&gt;&lt;P&gt;and clocks 24MHz,32.768KHz in both good and bad cases.&lt;/P&gt;&lt;P&gt;Check that ripple noise should be less than 5% Vp-p of supply voltage average value.&lt;/P&gt;&lt;P&gt;Also check if _CAP capacitors comply with latest recommendations below&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.nxp.com/docs/DOC-93819"&gt;HW Design Checking List for i.MX6DQSDL&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;~igor&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 12 Feb 2015 09:28:37 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/internal-boot-from-uSHC2/m-p/366701#M52055</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2015-02-12T09:28:37Z</dc:date>
    </item>
    <item>
      <title>Re: internal boot from uSHC2</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/internal-boot-from-uSHC2/m-p/366702#M52056</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;VDDARM_CAP: 1.17V (pk-pk ripple 0.84%)&lt;/P&gt;&lt;P&gt;VDDSOC_CAP: 1.17V (pk-pk ripple 3.4%)&lt;/P&gt;&lt;P&gt;VDDHIGH_CAP: 2.52V (pk-pk ripple 1.78%)&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;24MHz and 32.768KHzboth are in good shape&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;We have taken care whatever mention in the checklist.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;It is booting from SD-2 slot in boot mode 00. So I am just thinking, if there is any such issue, it should create problem there also. We are not able to get the clock or command signals itself. It means it is not even going to that step.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;With regards&lt;/P&gt;&lt;P&gt;LK&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 12 Feb 2015 15:08:04 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/internal-boot-from-uSHC2/m-p/366702#M52056</guid>
      <dc:creator>lk22</dc:creator>
      <dc:date>2015-02-12T15:08:04Z</dc:date>
    </item>
    <item>
      <title>Re: internal boot from uSHC2</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/internal-boot-from-uSHC2/m-p/366703#M52057</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;could you try to set BOOT_CFG2[5]=0 1-bit mode and check,&lt;/P&gt;&lt;P&gt;if it boots or any signal appears on SD bus ?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;~igor&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 12 Feb 2015 15:41:38 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/internal-boot-from-uSHC2/m-p/366703#M52057</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2015-02-12T15:41:38Z</dc:date>
    </item>
    <item>
      <title>Re: internal boot from uSHC2</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/internal-boot-from-uSHC2/m-p/366704#M52058</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I had already tried this. Bit there was no clock signal.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 12 Feb 2015 18:13:29 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/internal-boot-from-uSHC2/m-p/366704#M52058</guid>
      <dc:creator>lk22</dc:creator>
      <dc:date>2015-02-12T18:13:29Z</dc:date>
    </item>
    <item>
      <title>Re: internal boot from uSHC2</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/internal-boot-from-uSHC2/m-p/366705#M52059</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;- if this issue happens on one board or all (how many)&lt;/P&gt;&lt;P&gt;- could you provide full i.MX6 marking&lt;/P&gt;&lt;P&gt;- in bad case, does processor go to "Serial Downloader"&lt;/P&gt;&lt;P&gt;or just hangs ? If hangs, could you attach jtag and check where (address) ?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;~igor&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 13 Feb 2015 04:48:22 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/internal-boot-from-uSHC2/m-p/366705#M52059</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2015-02-13T04:48:22Z</dc:date>
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    <item>
      <title>Re: internal boot from uSHC2</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/internal-boot-from-uSHC2/m-p/366706#M52060</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;This issue happens on all boards&lt;/P&gt;&lt;P&gt;Full .MX6S marking:&lt;/P&gt;&lt;P&gt;MCIMX6S7CVM08AC&lt;/P&gt;&lt;P&gt;XAA1423&lt;/P&gt;&lt;P&gt;2N81E&lt;/P&gt;&lt;P&gt;TAIW AWAAXD&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;We don’t have OTG port. I think it hangs. I have to check on it.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;With regards&lt;/P&gt;&lt;P&gt;LK&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 13 Feb 2015 06:26:42 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/internal-boot-from-uSHC2/m-p/366706#M52060</guid>
      <dc:creator>lk22</dc:creator>
      <dc:date>2015-02-13T06:26:42Z</dc:date>
    </item>
    <item>
      <title>Re: internal boot from uSHC2</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/internal-boot-from-uSHC2/m-p/366707#M52061</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;also I would suggest to try check log buffer (usage described on link below),&lt;/P&gt;&lt;P&gt;with jtag check ROM address 0x000000d8, it contains pointer (0x00901AB8) to internal RAM &lt;/P&gt;&lt;P&gt;location where boot log buffer is stored. Can you send first 256 bytes of that buffer &lt;/P&gt;&lt;P&gt;for check.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.nxp.com/thread/307723"&gt;i.MX6Q NAND boot issues&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;~igor&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 13 Feb 2015 09:10:46 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/internal-boot-from-uSHC2/m-p/366707#M52061</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2015-02-13T09:10:46Z</dc:date>
    </item>
    <item>
      <title>Re: internal boot from uSHC2</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/internal-boot-from-uSHC2/m-p/366708#M52062</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;also please recheck that BOOT_CFG4[7]&lt;/P&gt;&lt;P&gt;(UART3_RTS ) not set to "1".&lt;/P&gt;&lt;P&gt;Table 8-2. Boot eFUSE Descriptions &lt;A href="http://cache.freescale.com/files/32bit/doc/ref_manual/IMX6SDLRM.pdf?fasp=1&amp;amp;WT_TYPE=Reference%20Manuals&amp;amp;WT_VENDOR=FREESCALE&amp;amp;WT_FILE_FORMAT=pdf&amp;amp;WT_ASSET=Documentation&amp;amp;fileExt=.pdf"&gt;IMX6SDLRM&lt;/A&gt; &lt;/P&gt;&lt;P&gt;BOOT_CFG4[7]=1&amp;nbsp; Infinite Loop Enable at start&lt;/P&gt;&lt;P&gt;of boot ROM. Used for debugging purposes.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 13 Feb 2015 14:32:33 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/internal-boot-from-uSHC2/m-p/366708#M52062</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2015-02-13T14:32:33Z</dc:date>
    </item>
    <item>
      <title>Re: internal boot from uSHC2</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/internal-boot-from-uSHC2/m-p/366709#M52063</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;BOOT_CFG4[7] is 1 as per original design. Only in one board we have changed it to 0, as per suggestion from Artur (tech support, Freescale).&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;With regards&lt;/P&gt;&lt;P&gt;LK&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 13 Feb 2015 14:48:55 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/internal-boot-from-uSHC2/m-p/366709#M52063</guid>
      <dc:creator>lk22</dc:creator>
      <dc:date>2015-02-13T14:48:55Z</dc:date>
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