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    <title>topic Re: I.MX6 Normal And Secure World RAM Address configuration in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/I-MX6-Normal-And-Secure-World-RAM-Address-configuration/m-p/366142#M51899</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi chiraq&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I think you can look at ARM resources devoted to this subject&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;A class="jive-link-external-small" href="http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.faqs/ka15417.html"&gt;http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.faqs/ka15417.html&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;A class="jive-link-external-small" href="http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.prd29-genc-009492c/index.html"&gt;http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.prd29-genc-009492c/index.html&lt;/A&gt;&lt;/P&gt;&lt;P&gt;MX6 Security Reference Manual on&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.nxp.com/docs/DOC-97660"&gt;Q&amp;amp;amp;A: How is mx6 PMIC_ON_REQ under SW control?&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;&lt;P&gt;igor&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 26 Nov 2014 04:19:37 GMT</pubDate>
    <dc:creator>igorpadykov</dc:creator>
    <dc:date>2014-11-26T04:19:37Z</dc:date>
    <item>
      <title>I.MX6 Normal And Secure World RAM Address configuration</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/I-MX6-Normal-And-Secure-World-RAM-Address-configuration/m-p/366141#M51898</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi all,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I am trying to enable Trustzone features for i.mx6 saberlite board in OS. At this stage, I am stuck with a problem.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I am not able to locate Normal world RAM address to load second OS.&lt;/P&gt;&lt;P&gt;so some one help me to configure NORMAL and SECURE mode RAM address.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks in Advance,&lt;/P&gt;&lt;P&gt;Chirag :smileyhappy:&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 24 Nov 2014 19:27:18 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/I-MX6-Normal-And-Secure-World-RAM-Address-configuration/m-p/366141#M51898</guid>
      <dc:creator>chiraggarg</dc:creator>
      <dc:date>2014-11-24T19:27:18Z</dc:date>
    </item>
    <item>
      <title>Re: I.MX6 Normal And Secure World RAM Address configuration</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/I-MX6-Normal-And-Secure-World-RAM-Address-configuration/m-p/366142#M51899</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi chiraq&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I think you can look at ARM resources devoted to this subject&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;A class="jive-link-external-small" href="http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.faqs/ka15417.html"&gt;http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.faqs/ka15417.html&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;A class="jive-link-external-small" href="http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.prd29-genc-009492c/index.html"&gt;http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.prd29-genc-009492c/index.html&lt;/A&gt;&lt;/P&gt;&lt;P&gt;MX6 Security Reference Manual on&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.nxp.com/docs/DOC-97660"&gt;Q&amp;amp;amp;A: How is mx6 PMIC_ON_REQ under SW control?&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;&lt;P&gt;igor&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 26 Nov 2014 04:19:37 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/I-MX6-Normal-And-Secure-World-RAM-Address-configuration/m-p/366142#M51899</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2014-11-26T04:19:37Z</dc:date>
    </item>
    <item>
      <title>Re: I.MX6 Normal And Secure World RAM Address configuration</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/I-MX6-Normal-And-Secure-World-RAM-Address-configuration/m-p/366143#M51900</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Yes , I have gone through these links..&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Actually I have enabled the switching b/w the Normal and Secure world. So when it is switching from secure world OS to the Normal world OS. It is giving &lt;STRONG&gt;IO mapped failed error. &lt;/STRONG&gt;so i guess RAM configuration for Normal World is not correct.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;so i need RAM configuration for Normal world in imx6 saberlite board.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks in Advance,&lt;/P&gt;&lt;P&gt;CHIRAG&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 26 Nov 2014 05:20:41 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/I-MX6-Normal-And-Secure-World-RAM-Address-configuration/m-p/366143#M51900</guid>
      <dc:creator>chiraggarg</dc:creator>
      <dc:date>2014-11-26T05:20:41Z</dc:date>
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