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    <title>topic SD_RST (on USDHC3 and USDHC4 only) in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/SD-RST-on-USDHC3-and-USDHC4-only/m-p/364997#M51652</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P style="font-size: 13.3333330154419px;"&gt;Hi,&lt;/P&gt;&lt;P style="font-size: 13.3333330154419px;"&gt;&lt;/P&gt;&lt;P style="font-size: 13.3333330154419px;"&gt;As mentioned in IMX6SLRM , Table 8-11. :&lt;/P&gt;&lt;P style="font-size: 13.3333330154419px;"&gt;"eMMC reset enabled via SD_RST pad (on USDHC3 and USDHC4 only)"&lt;/P&gt;&lt;P style="font-size: 13.3333330154419px;"&gt;&lt;/P&gt;&lt;P style="font-size: 13.3333330154419px;"&gt;1. So does it mean, if eMMC is mounted in SoloLite EVK then whenever Por_b is asserted then the eMMC will not reset since SD2 is used ? &lt;/P&gt;&lt;P style="font-size: 13.3333330154419px;"&gt;&lt;/P&gt;&lt;P style="font-size: 13.3333330154419px;"&gt;2. eMMC reset won't be availble if using USDHC1 and USDHC2 ?&lt;/P&gt;&lt;P style="font-size: 13.3333330154419px;"&gt;&lt;/P&gt;&lt;P style="font-size: 13.3333330154419px;"&gt;Please clarify. Thanks.&lt;/P&gt;&lt;P style="font-size: 13.3333330154419px;"&gt;&lt;/P&gt;&lt;P style="font-size: 13.3333330154419px;"&gt;--Pankaj Rana&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Fri, 06 Mar 2015 12:18:29 GMT</pubDate>
    <dc:creator>pankajrana</dc:creator>
    <dc:date>2015-03-06T12:18:29Z</dc:date>
    <item>
      <title>SD_RST (on USDHC3 and USDHC4 only)</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/SD-RST-on-USDHC3-and-USDHC4-only/m-p/364997#M51652</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P style="font-size: 13.3333330154419px;"&gt;Hi,&lt;/P&gt;&lt;P style="font-size: 13.3333330154419px;"&gt;&lt;/P&gt;&lt;P style="font-size: 13.3333330154419px;"&gt;As mentioned in IMX6SLRM , Table 8-11. :&lt;/P&gt;&lt;P style="font-size: 13.3333330154419px;"&gt;"eMMC reset enabled via SD_RST pad (on USDHC3 and USDHC4 only)"&lt;/P&gt;&lt;P style="font-size: 13.3333330154419px;"&gt;&lt;/P&gt;&lt;P style="font-size: 13.3333330154419px;"&gt;1. So does it mean, if eMMC is mounted in SoloLite EVK then whenever Por_b is asserted then the eMMC will not reset since SD2 is used ? &lt;/P&gt;&lt;P style="font-size: 13.3333330154419px;"&gt;&lt;/P&gt;&lt;P style="font-size: 13.3333330154419px;"&gt;2. eMMC reset won't be availble if using USDHC1 and USDHC2 ?&lt;/P&gt;&lt;P style="font-size: 13.3333330154419px;"&gt;&lt;/P&gt;&lt;P style="font-size: 13.3333330154419px;"&gt;Please clarify. Thanks.&lt;/P&gt;&lt;P style="font-size: 13.3333330154419px;"&gt;&lt;/P&gt;&lt;P style="font-size: 13.3333330154419px;"&gt;--Pankaj Rana&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 06 Mar 2015 12:18:29 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/SD-RST-on-USDHC3-and-USDHC4-only/m-p/364997#M51652</guid>
      <dc:creator>pankajrana</dc:creator>
      <dc:date>2015-03-06T12:18:29Z</dc:date>
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    <item>
      <title>Re: SD_RST (on USDHC3 and USDHC4 only)</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/SD-RST-on-USDHC3-and-USDHC4-only/m-p/364998#M51653</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Pankaj&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;1. Por_b does not affect SD_RST. eMMC will be reset by Power Cycle&lt;/P&gt;&lt;P&gt;or SD_RST (H/W RESET) according to emmc specifications.&lt;/P&gt;&lt;P&gt;2. if using USDHC1 and USDHC2 only Power Cycle reset is available.&lt;/P&gt;&lt;P&gt;In general one can use any gpio for usage as SD_RST.&lt;/P&gt;&lt;P&gt;Details about SD_RST can be found on link below&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.nxp.com/thread/338915"&gt;About SDa_RST_B (SD3_RST) signal in i.MX6.&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;&lt;P&gt;igor&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;P&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sat, 07 Mar 2015 15:22:22 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/SD-RST-on-USDHC3-and-USDHC4-only/m-p/364998#M51653</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2015-03-07T15:22:22Z</dc:date>
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