topic Re: Parallel CSI not working (as expected) in i.MX Processors

Parallel CSI not working (as expected)

davider — Fri, 21 Nov 2014 12:37:10 GMT

I'm writing a driver for a custom FPGA based frame grabber, connected to an i.MX6D (IPU1 CSI0) with an 8 (16) bit parallel interface. The kernel is Linux-3.10.17-1.0.1.

The interface comprises the 16 MSB, HSYNC, VSYNC, PIXCLK. DATA_EN is not connected to the FPGA, but it is accessible.

The pin muxing seems ok (checked with a JTAG debugger), the pins are connected (I can see them moving on GPIO5).

For the driver code, I have modified the OV5640 driver, removing all the i2c stuff, and keeping only the v4l related code.

The kernel module gets loaded, everything works as expected in terms of ioctls, but when I try to display the data coming from the interface I get a "ERROR: v4l2 capture: mxc_v4l_dqueue timeout enc_counter 0"...

If I turn on the pattern generator, I can see the IDMA channel 0 EOF and NFACK Interrupts moving, I can even see the checkerboard (the colors are not quite right, but I will investigate this problem later). If I turn it off, nothing happens.

I have pulled DATA_EN high, and have tried both the "gated" and "non gated" modes, either with a short or long (all frame long) VSYNC.

Beside the setup and hold times, specified in the datasheets, are there any other timing constraints to consider?

Any idea? :smileyhappy:

Thank you!

EDIT:

There was a problem with the IDMAC buffers, that where configured for a YUV420 stream, but the FPGA is producing a RGB888 stream. I was not able to correct the problem at camera driver level, so I overrode the pixelformat in mxc_v4l2_s_fmt, and now it seems ok (640x480 - 1920 stride).

But I still get the timeout error, and the EOF/NFACK interrupts keep cleared all the time.

I am reasonably sure the FPGA is producing the correct waveforms (non gated mode), according to the documentation.

Any idea and/or suggestion?

SOLVED!!!

IOMUXC_GPR1.MIPI_IPU1_MUX was the problem. It was 0.

Re: Parallel CSI not working (as expected)

davider — Mon, 24 Nov 2014 12:31:46 GMT

Just an update: is the MCLK (output) really needed? Can the sensor use it's own clock?

Is there an implementation of a Test Pattern Generator driver I can use as a reference to check that my own implementation is ok?

Re: Parallel CSI not working (as expected)

satheshkumarman — Tue, 25 Nov 2014 05:40:54 GMT

Set SION filed to ZERO in IOMUX of CSI0_DATA_EN

Reverse the polarity of CSI0_DATA_EN_POL filed of IPUx_CSI0_SENS_CONF

Thanks.

Re: Parallel CSI not working (as expected)

davider — Wed, 26 Nov 2014 12:39:55 GMT

I've already tried it, and I'm really sorry to say that it does not work...

A couple more questions.

What does exactly do the Test Gen Mode in TST_CTRL do?

Must the NFACK move on every new frame (VSYNC)?

Re: Parallel CSI not working (as expected)

ozzyromero — Wed, 21 Jan 2015 02:03:09 GMT

Hi Davide,

I am trying to also get video from an FPGA via the parallel CSI0 port on the iMX6 Quad.

When you removed all the I2C related code what did you do with the read's? Did you spoof the values?

What else did you besides remove I2C code?

Any help would greatly be appreciated.

Thanks!

Ozzy