topic Re: I.MX28 Linux Arm Alignment Trap in i.MX Processors

I.MX28 Linux Arm Alignment Trap

nathanb_ — Wed, 04 Mar 2015 13:24:50 GMT

Hello All,

We are currently investigating processors to use in a new product design. I've written some sample code that compiles (with GCC under Linux) and runs seamlessly on ARM Cortex A9 processors from various semiconductor manufacturers (I.MX6, ...) .

When running this code on an I.MX28 EVK, the code seems to function. However, it's slow. It gives a few thousand of these messages in the process of running the test:

Alignment trap: test (29858) PC=... Instr=... Address=... FSR ...

Looking at the GCC manual, there are mentions of unaligned access traps being enabled and disabled with the -malignment-traps and -mno-alignment-traps options. However, it says that these options do not effect ARM architecture 4 or later.

The I.MX28 ARM9 architecture is ARMv5, while Cortex A9 is ARMv7. Both of these are above architecture 4.

Does anyone have any insight into what could be going on here? What's the difference between these two architectures?

We could change the code to explicitly access memory on even boundaries, but if it is unnecessary on newer ARM architectures then we could prefer not to design for an older architecture.

Thanks

Re: I.MX28 Linux Arm Alignment Trap

Yuri — Thu, 05 Mar 2015 05:47:58 GMT

“For processors based on ARMv5 or earlier, or ARMv6-M, you must ensure that addresses
for 4-byte transfers are 4-byte word-aligned, and addresses for 2-byte transfers are 2-byte
aligned. In ARMv6 and later, except ARMv6-M, unaligned accesses are permitted for LDR,
LDRH, STR, STRH, LDRSH, LDRT, STRT, LDRSHT, LDRHT, STRHT, and TBH instructions,
where the architecture supports the instruction”.

< http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0473c/Cihdbfje.html >

Have a great day,
Yuri

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Re: I.MX28 Linux Arm Alignment Trap

nathanb_ — Thu, 26 Mar 2015 18:13:13 GMT

Thanks