topic Re: MX6SL Power up without OFF mode support in i.MX Processors

MX6SL Power up without OFF mode support

nathanpalmer — Fri, 27 Mar 2015 13:01:25 GMT

I have had problems booting a board with an MX6SL CPU + PF0100 PMIC. As a workaround, we have removed support for the SNVS domain by making the following design changes. I think that all of them are supported by the official Freescale documentation, but I wanted to ask the community if there is anything that I am missing:

See: SR 1-3679179854 and https://community.freescale.com/message/449238

1) Can I short VDD_HIGH_IN to VDD_SNVS_IN external to the MX6SL and drive them both with the SW2 (3.15V) output of the PF0100 PMIC?

2) Can I force the PMIC to be "always on" by shorting PWRON to SNVS on the PF0100?

I think those two things will fix the boot problem at the expense of no longer supporting the SNVS power mode on the MX6SL. Any gotchas to look out for?

Thanks!

Re: MX6SL Power up without OFF mode support

igorpadykov — Fri, 27 Mar 2015 14:47:30 GMT

Hi Nathan

I believe yes, answer is positive for both questions.

PMIC start-up behaviour greatly depends on presence LICELL

(coin cell) and it is described in datasheet.

Best regards

igor

Re: MX6SL Power up without OFF mode support

nathanpalmer — Fri, 27 Mar 2015 14:59:19 GMT

Great, thanks. I have read the data sheets a lot over the last few months :smileyhappy:

One final question on this:

3) The STANDBY pin is driven directly from the MX6SL (PMIC_STBY_REQ pin) to the PF0100 PMIC. Is there a concern that the PMIC_STBY_REQ, which is now IO un-powered until SW2 is powered, will be in-valid and cause an unpredictable level on the PMIC STANDBY pin at start up, i.e. before SW2 has powered the MX6SL SNVS domain?

Re: MX6SL Power up without OFF mode support

igorpadykov — Fri, 27 Mar 2015 15:21:55 GMT

PMIC STANDBY will take effect when PMIC will be operational,

fully powered.

Re: MX6SL Power up without OFF mode support

nathanpalmer — Fri, 27 Mar 2015 19:13:10 GMT

Thanks for the response.

Then there may be a problem, as shown in this figure. What does "fully powered" mean in the PMIC? I think you mean that the PMIC is in the ON state, which I think happens when SNVS pulls PWRON high (in my design). If STANDBY is sampled before SW2 goes high, then it may be invalid because the MX6 SNVS IO domain is not powered. Is there an internal pull-up/down etc. on the STANDBY pin to prevent problems?

Re: MX6SL Power up without OFF mode support

igorpadykov — Sat, 28 Mar 2015 00:47:42 GMT

"fully powered" mean ON state, RESETBMCU does high on Figure 6 MMPF0100

STANDBY can not be sampled before SW2 goes high, because PMIC

should be in the ON state - this means that SW2 will be in normal state, high.

MMPF0100 Figure 8. State Diagram, Table 22. Standby Pin and Polarity Control

foot note 33 - The state of the STANDBY pin only has influence in On mode.

Re: MX6SL Power up without OFF mode support

nathanpalmer — Sat, 28 Mar 2015 14:05:44 GMT

Great, thanks. I was concerned that the ON state was entered as soon a SNVS pulled PWRON high. Good to know that ON is only entered after all rails are up.