<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>i.MX ProcessorsのトピックRe: MMPF0100 register value after reading &amp;quot;Default Configuration&amp;quot; or &amp;quot;OTP&amp;quot;.</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/MMPF0100-register-value-after-reading-quot-Default-Configuration/m-p/353348#M49282</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;A1. By default, the values of the SWxxSTBY and SWxxOFF registers are equal to the SWxxVOLT registers according to the selected start-up configuration. After startup, the software can change the SWxxSTBY and SWxxOFF registers to the appropriate values.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;A2. Yes, this is correct.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;A3. The VREFDDR linear regulator is always enabled by default. For the VGENx linear regulators, it depends on the start-up configuration selected, please refer to the Table 10 of the PF0100 Data Sheet.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;A4. The VGEN1[3:0] = 0b1110 and VGEN3[3:0] = 0b0111 for the Default configuration. However, these values are meaningless, since the VGEN1 and VGEN3 regulators are disabled at start-up in the Default configuration.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;A5. The SWDVS_CLK value applies not to the power-up sequence, but to the Dynamic Voltage Scaling (DVS) operation during normal system run. This value is applied to all switching regulators.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Have a great day,&lt;BR /&gt;Artur&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 15 Jan 2015 11:28:17 GMT</pubDate>
    <dc:creator>art</dc:creator>
    <dc:date>2015-01-15T11:28:17Z</dc:date>
    <item>
      <title>MMPF0100 register value after reading "Default Configuration" or "OTP".</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/MMPF0100-register-value-after-reading-quot-Default-Configuration/m-p/353346#M49280</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi community,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I'm cheking the value of MMPF0100 registers after read "Default Configuration" or "OTP" setting as attached file.&lt;/P&gt;&lt;P&gt;I input the values refer to Table 10 of MMPF0100 datasheet (Rev.9.0).&lt;/P&gt;&lt;P&gt;However, I did not understand the value of SWxxSTBY, SWxxOFF, xxxxCTL registers (highlighted registers).&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;[Q1]&lt;/P&gt;&lt;P&gt;Would you let me know the setting value of each SWxxSTBY and SWxxOFF register?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;[Q2]&lt;/P&gt;&lt;P&gt;According to Table 88, I guess SWBSTCTL value is 0100_1000b in both case "Default Configuration" is read or "F0 OTP" is read.&lt;/P&gt;&lt;P&gt;Is this correct?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;[Q3]&lt;/P&gt;&lt;P&gt;I believe the enable bit of VREFDDRCTL and VGENxCTL bit (bit [4]) is "1".&lt;/P&gt;&lt;P&gt;Is this correct?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;[Q4]&lt;/P&gt;&lt;P&gt;Could you let me know the setting value of VGEN1[3:0] and VGEN3[3:0] after read "Default Configuration"? (red characters)&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;[Q5]&lt;/P&gt;&lt;P&gt;According to Table 10, SWDVS_CLK is "6.25 mV/us" for "Default Configuration" and "1.5625 mV/us" for "F0".&lt;/P&gt;&lt;P&gt;So I understand this setting is applied to all switching regulators as below, is this correct?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Default Configuration: 25mV/4.0us for SW1x, 50mV/8.0us for SW2, SW3A/B, and SW4.&lt;/P&gt;&lt;P&gt;F0: 25mV/16us for SW1x, 50mV/32us for SW2, SW3A/B, and SW4.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best Regards,&lt;/P&gt;&lt;P&gt;Satoshi Shimoda&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 16 Dec 2014 05:45:26 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/MMPF0100-register-value-after-reading-quot-Default-Configuration/m-p/353346#M49280</guid>
      <dc:creator>satoshishimoda</dc:creator>
      <dc:date>2014-12-16T05:45:26Z</dc:date>
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    <item>
      <title>Re: MMPF0100 register value after reading "Default Configuration" or "OTP".</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/MMPF0100-register-value-after-reading-quot-Default-Configuration/m-p/353347#M49281</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Would you reply to my question?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 09 Jan 2015 07:30:14 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/MMPF0100-register-value-after-reading-quot-Default-Configuration/m-p/353347#M49281</guid>
      <dc:creator>satoshishimoda</dc:creator>
      <dc:date>2015-01-09T07:30:14Z</dc:date>
    </item>
    <item>
      <title>Re: MMPF0100 register value after reading "Default Configuration" or "OTP".</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/MMPF0100-register-value-after-reading-quot-Default-Configuration/m-p/353348#M49282</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;A1. By default, the values of the SWxxSTBY and SWxxOFF registers are equal to the SWxxVOLT registers according to the selected start-up configuration. After startup, the software can change the SWxxSTBY and SWxxOFF registers to the appropriate values.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;A2. Yes, this is correct.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;A3. The VREFDDR linear regulator is always enabled by default. For the VGENx linear regulators, it depends on the start-up configuration selected, please refer to the Table 10 of the PF0100 Data Sheet.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;A4. The VGEN1[3:0] = 0b1110 and VGEN3[3:0] = 0b0111 for the Default configuration. However, these values are meaningless, since the VGEN1 and VGEN3 regulators are disabled at start-up in the Default configuration.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;A5. The SWDVS_CLK value applies not to the power-up sequence, but to the Dynamic Voltage Scaling (DVS) operation during normal system run. This value is applied to all switching regulators.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Have a great day,&lt;BR /&gt;Artur&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 15 Jan 2015 11:28:17 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/MMPF0100-register-value-after-reading-quot-Default-Configuration/m-p/353348#M49282</guid>
      <dc:creator>art</dc:creator>
      <dc:date>2015-01-15T11:28:17Z</dc:date>
    </item>
    <item>
      <title>Re: MMPF0100 register value after reading "Default Configuration" or "OTP".</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/MMPF0100-register-value-after-reading-quot-Default-Configuration/m-p/353349#M49283</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Artur,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thank you for your reply.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;gt; A1, 2, 3, 4&lt;/P&gt;&lt;P&gt;OK, I understood.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;gt;A5. The SWDVS_CLK value applies not to the power-up sequence, but to the Dynamic Voltage Scaling (DVS) operation during normal system run. &lt;/P&gt;&lt;P&gt;Yes, but I think the SWDVS_CLK OTP value is applied to SWxCONFIG[7:6] even though these are not used when power-up sequence.&lt;/P&gt;&lt;P&gt;Is this correct?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;gt; This value is applied to all switching regulators.&lt;/P&gt;&lt;P&gt;OK, I understood.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best Regards,&lt;/P&gt;&lt;P&gt;Satoshi Shimoda&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 16 Jan 2015 04:23:28 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/MMPF0100-register-value-after-reading-quot-Default-Configuration/m-p/353349#M49283</guid>
      <dc:creator>satoshishimoda</dc:creator>
      <dc:date>2015-01-16T04:23:28Z</dc:date>
    </item>
    <item>
      <title>Re: MMPF0100 register value after reading "Default Configuration" or "OTP".</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/MMPF0100-register-value-after-reading-quot-Default-Configuration/m-p/353350#M49284</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Q. The SWDVS_CLK OTP value is applied to SWxCONFIG[7:6] even though these are not used when power-up sequence. Is this correct?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;A. Yes, this is correct.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Have a great day,&lt;BR /&gt;Artur&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 19 Jan 2015 09:56:55 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/MMPF0100-register-value-after-reading-quot-Default-Configuration/m-p/353350#M49284</guid>
      <dc:creator>art</dc:creator>
      <dc:date>2015-01-19T09:56:55Z</dc:date>
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  </channel>
</rss>

