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    <title>topic Re: Question, i.MX6D PMIC_STBY_REQ in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6D-PMIC-STBY-REQ/m-p/353088#M49229</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P style="padding: 0 0 24.0pt 0;"&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;&amp;nbsp;&amp;nbsp; Strictly speaking, pin states of i.MX6 during power on sequence and POR &lt;BR /&gt;are not defined. In the same time, the PMIC_STBY_REQ of the i.MX6 and &lt;BR /&gt;corresponding PMIC MMPF0100 STANDBY signals are fed via coin cell (always&amp;nbsp;&amp;nbsp; &lt;BR /&gt;present) VSNVS supply. So, undefined state of the PMIC_STBY_REQ may&lt;BR /&gt;take place only when changing the coin cell. Note, after reset the PMIC_STBY_REQ &lt;BR /&gt;is negated (LOW) and the PMIC exits standby mode.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;Have a great day,&lt;BR /&gt;Yuri&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Mon, 27 Oct 2014 05:25:27 GMT</pubDate>
    <dc:creator>Yuri</dc:creator>
    <dc:date>2014-10-27T05:25:27Z</dc:date>
    <item>
      <title>Question, i.MX6D PMIC_STBY_REQ</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6D-PMIC-STBY-REQ/m-p/353087#M49228</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Dear team,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I would like to ask about the behavior of i.MX6D PMIC_STBY_REQ.&lt;/P&gt;&lt;P&gt;My customer is trying to add external WatchDog for the workaround of ERR006282.&lt;/P&gt;&lt;P&gt;They tested whether the watchdog can work fine in the case of boot failure by forced removing input to the WD.&lt;/P&gt;&lt;P&gt;And they saw some i.MX6 chips did output High from PMIC_STBY_REQ when POR = L, and some chips did not.&lt;/P&gt;&lt;P&gt;They expected i.MX6 does not output High from PMIC_STBY_REQ when POR gets asserted.&lt;/P&gt;&lt;P&gt;Is the behavior of PMIC_STBY_REQ reasonable?&lt;/P&gt;&lt;P&gt;Are there any ways to make i.MX6 not output High from PMIC_STBY_REQ at POR=L?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;BTW, the customer uses &lt;SPAN lang="EN-US" style="font-size: 10.5pt; font-family: 'Arial','sans-serif';"&gt;MCIMX6D7CVT08AC.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks,&lt;/P&gt;&lt;P&gt;Miyamoto&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 27 Oct 2014 02:57:59 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6D-PMIC-STBY-REQ/m-p/353087#M49228</guid>
      <dc:creator>Aemj</dc:creator>
      <dc:date>2014-10-27T02:57:59Z</dc:date>
    </item>
    <item>
      <title>Re: Question, i.MX6D PMIC_STBY_REQ</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6D-PMIC-STBY-REQ/m-p/353088#M49229</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P style="padding: 0 0 24.0pt 0;"&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;&amp;nbsp;&amp;nbsp; Strictly speaking, pin states of i.MX6 during power on sequence and POR &lt;BR /&gt;are not defined. In the same time, the PMIC_STBY_REQ of the i.MX6 and &lt;BR /&gt;corresponding PMIC MMPF0100 STANDBY signals are fed via coin cell (always&amp;nbsp;&amp;nbsp; &lt;BR /&gt;present) VSNVS supply. So, undefined state of the PMIC_STBY_REQ may&lt;BR /&gt;take place only when changing the coin cell. Note, after reset the PMIC_STBY_REQ &lt;BR /&gt;is negated (LOW) and the PMIC exits standby mode.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;Have a great day,&lt;BR /&gt;Yuri&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 27 Oct 2014 05:25:27 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6D-PMIC-STBY-REQ/m-p/353088#M49229</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2014-10-27T05:25:27Z</dc:date>
    </item>
    <item>
      <title>Re: Question, i.MX6D PMIC_STBY_REQ</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6D-PMIC-STBY-REQ/m-p/353089#M49230</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Yuri,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks for your reply.&lt;/P&gt;&lt;P&gt;What the customer wants to do is to reset i.MX6 without asserting PMIC_STBY_REQ.&lt;/P&gt;&lt;P&gt;Do you have any ideas on that?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;BestRegards,&lt;/P&gt;&lt;P&gt;Miyamoto&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 27 Oct 2014 08:25:14 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6D-PMIC-STBY-REQ/m-p/353089#M49230</guid>
      <dc:creator>Aemj</dc:creator>
      <dc:date>2014-10-27T08:25:14Z</dc:date>
    </item>
    <item>
      <title>Re: Question, i.MX6D PMIC_STBY_REQ</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6D-PMIC-STBY-REQ/m-p/353090#M49231</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P style="padding: 0 0 24.0pt 0;"&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;&amp;nbsp;&amp;nbsp; The erratum workaround provides general idea how to usean external watchdog :&lt;BR /&gt;"The user implements an external watchdog [...]. On a successful boot,&lt;BR /&gt;the processor toggles the external watchdog through some I/O mechanism&lt;BR /&gt;(for example, a GPIO) which prevents the watchdog from firing. If a boot failure&lt;BR /&gt;occurs, the external watchdog will expire, thus resetting the processor."&lt;BR /&gt;&amp;nbsp;&amp;nbsp; Unpredictable GPIO pin states should not take place when using MX6 POR signal&lt;BR /&gt;for reset under stable power supply voltages (voltage rising has been&amp;nbsp; finished).&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="padding: 0 0 24.0pt 0;"&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;~Yuri.&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="padding: 0 0 24.0pt 0;"&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 27 Oct 2014 11:56:47 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6D-PMIC-STBY-REQ/m-p/353090#M49231</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2014-10-27T11:56:47Z</dc:date>
    </item>
    <item>
      <title>Re: Question, i.MX6D PMIC_STBY_REQ</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6D-PMIC-STBY-REQ/m-p/353091#M49232</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Thanks Yuri.&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 10pt; line-height: 1.5em;"&gt;&amp;gt; Using MX6 POR signal for reset under stable power supply voltages(voltage rising has been finished).&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;As for the above, &lt;/P&gt;&lt;P&gt;Can I understand PMIC_STBY_REQ signal should be disconnected from MMPF0100 in the above situation at least?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;BR,&lt;/P&gt;&lt;P&gt;Miyamoto&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 27 Oct 2014 16:55:02 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6D-PMIC-STBY-REQ/m-p/353091#M49232</guid>
      <dc:creator>Aemj</dc:creator>
      <dc:date>2014-10-27T16:55:02Z</dc:date>
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