topic Re: Reset PLL2 and PLL3 in i.MX Processors

Reset PLL2 and PLL3

christianbach — Mon, 15 Dec 2014 15:51:16 GMT

CPU boots from DDR Ram and i try to reset PLL2 and PLL3 with the following steps:

1. store clock registers

2. remap PLL2 clocks to PLL3

3. power down PLL2

4. reintialize PLL2 with PFDs

5. remap PLL3 clocks to PLL2

6. power down PLL3

7. reintialize PLL2 with PFDs

8. restore clock registers

At Step 1 when i switch CBCDR[periph_clk_sel] from PLL2 (528Mhz) to PLL3 (480) Mhz, the system crashes. What can i do to switch AHB and MMDC_CH0 to PLL3?

Re: Reset PLL2 and PLL3

igorpadykov — Tue, 16 Dec 2014 00:59:02 GMT

Hi Christian

PLL2 usually is used for DDR (MMDC module), so if program

runs from DDR, it is not possible to change clock (or source of clock)

of MMDC module. One needs to put DDR to self-refresh, jump to iRAM,

switch/change clocks for MMDC, then return to normal operation from DDR.

In general also crash can be caused by PFD gating, described in

EB790 Configuration of Phase Fractional Dividers

Best regards

igor

-----------------------------------------------------------------------------------------------------------------------

Note: If this post answers your question, please click the Correct Answer button. Thank you!

-----------------------------------------------------------------------------------------------------------------------

Re: Reset PLL2 and PLL3

christianbach — Tue, 16 Dec 2014 08:17:26 GMT

Hello igor,

thank you for your help.