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    <title>i.MX ProcessorsのトピックRe: LPDDR2 config on imx6sl</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/LPDDR2-config-on-imx6sl/m-p/348775#M48323</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi igor&lt;/P&gt;&lt;P&gt;I have tried what you said,the result is &lt;/P&gt;&lt;P&gt;HAB_TYPE: DEVELOP&lt;/P&gt;&lt;P&gt;rom_write: reading HAB ack failed 0x00000000&lt;/P&gt;&lt;P&gt;ROM Write failed, addr: 0x021b001c&lt;/P&gt;&lt;P&gt;Write dcd failed.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;and I know MMDC valid addr start from 0x021B0000,but your Aid can automatically generate the Inc, I cannot motify it because I dont know whether it is right after motifying it.&lt;/P&gt;&lt;P&gt;So could you give me another help? 3q very much!&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 05 Feb 2015 10:16:12 GMT</pubDate>
    <dc:creator>tony_l_cai</dc:creator>
    <dc:date>2015-02-05T10:16:12Z</dc:date>
    <item>
      <title>LPDDR2 config on imx6sl</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/LPDDR2-config-on-imx6sl/m-p/348771#M48319</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,All&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; Maybe, some params in LPDDR2 Aid is not right,so when I use the DDR stress tool, test is failed.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; So I want to know some definition about the options in Aid. &lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; DRAM single Die density，How to know how many dies is in this LPDDR2. Some datasheet didnt show it clearly. &lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; Number of chip selects used, How to know in datasheet.&amp;nbsp; I cant find the clear answers in datasheet,either.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; So could you give me more help,and make Aid can pass the DDR stress test.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; our LPDDR2 is winbond W97BH2KBQX2I，and the LPDDR2 datasheet and Aid settings are following. &lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; After ddr stress test ，the result is following. I want to know If the DDR can not work??&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; Dont to tell me where the DDR controller addr is ,and the following is not. so the DDR settings is not right.&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 10pt; line-height: 1.5em;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; But before this LPDDR2, we also use a LPDDR2, in inc, the DDR controller addr is the same with this DDR,and the former one can work.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 10pt; line-height: 1.5em;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; so I just want to say, maybe some other factors make this DDR can not work. Please help me, thank you very much !&amp;nbsp;&amp;nbsp; &lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 04 Feb 2015 14:45:26 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/LPDDR2-config-on-imx6sl/m-p/348771#M48319</guid>
      <dc:creator>tony_l_cai</dc:creator>
      <dc:date>2015-02-04T14:45:26Z</dc:date>
    </item>
    <item>
      <title>Re: LPDDR2 config on imx6sl</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/LPDDR2-config-on-imx6sl/m-p/348772#M48320</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;&amp;nbsp; Please look at my comments below.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;1.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;&amp;nbsp; Please refer to section 2 (DDR3 initialization Script Generation Aid) of the &lt;BR /&gt; Porting Guide for more details regarding Script Generation Aid using. &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;&lt;A class="" data-containerid="-1" data-containertype="-1" data-objectid="278514" data-objecttype="13" href="https://community.freescale.com/servlet/JiveServlet/download/101708-1-278514/Freescale+i.MX6+DRAM+Port+Application+Guide-DDR3.pdf"&gt;https://community.freescale.com/servlet/JiveServlet/download/101708-1-278514/Freescale%20i.MX6%20DRAM%20Port%20Application%20Guide-DDR3.pdf&lt;/A&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;&lt;A class="jive-link-wiki-small" data-containerid="2004" data-containertype="14" data-objectid="101708" data-objecttype="102" href="https://community.freescale.com/docs/DOC-101708"&gt;https://community.freescale.com/docs/DOC-101708&lt;/A&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;2.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt; It looks like two CS(s) and 32-bit data bus are applied in the case.&lt;BR /&gt; Is it so (four W97BH2KBQX2I parts) ?&amp;nbsp; In such case “DRAM density per CS”&lt;BR /&gt; is 4 (Gb).&lt;BR /&gt; &lt;BR /&gt; (if possible, please provide connection scheme between i.MX6 SL and DRAMs.)&amp;nbsp;&amp;nbsp; &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;3.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;&amp;nbsp; According to the DRAM Datasheet “number of COLUMN addresses” is 10.&lt;BR /&gt; &lt;BR /&gt; &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;4.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;You may try to adjust drive strength options. &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;&lt;A class="jive-link-thread-small" data-containerid="2004" data-containertype="14" data-objectid="338460" data-objecttype="1" href="https://community.freescale.com/thread/338460"&gt;https://community.freescale.com/thread/338460&lt;/A&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Have a great day,&lt;BR /&gt;Yuri&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 05 Feb 2015 08:41:33 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/LPDDR2-config-on-imx6sl/m-p/348772#M48320</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2015-02-05T08:41:33Z</dc:date>
    </item>
    <item>
      <title>Re: LPDDR2 config on imx6sl</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/LPDDR2-config-on-imx6sl/m-p/348773#M48321</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Yuri,&lt;/P&gt;&lt;P&gt;         2. only one w97bh2kbq2i part, why are 4 parts? Where  did you get this info about 4 parts?&lt;/P&gt;&lt;P&gt;         3. In datasheet,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;         Column addr C0-C8,so number of Column addr ,why is 10,not 9  ?  How to get 10?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;发件人: Yuri Muhin &lt;/P&gt;&lt;P&gt;发送时间: 2015年2月5日 16:43&lt;/P&gt;&lt;P&gt;收件人: Tony L Cai&lt;/P&gt;&lt;P&gt;主题: Re:  - LPDDR2 config on imx6sl&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;lt;https://community.freescale.com/&amp;gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;LPDDR2 config on imx6sl&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;reply from Yuri Muhin&amp;lt;https://community.freescale.com/people/Yuri?et=watches.email.thread&amp;gt; in i.MX Community - View the full discussion&amp;lt;https://community.freescale.com/message/477807?et=watches.email.thread#477807&amp;gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 05 Feb 2015 09:09:00 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/LPDDR2-config-on-imx6sl/m-p/348773#M48321</guid>
      <dc:creator>tony_l_cai</dc:creator>
      <dc:date>2015-02-05T09:09:00Z</dc:date>
    </item>
    <item>
      <title>Re: LPDDR2 config on imx6sl</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/LPDDR2-config-on-imx6sl/m-p/348774#M48322</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi tony&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;this LPDDR2 is single die. Error in attached file:&lt;/P&gt;&lt;P&gt;"dcd address 0x020bc000 out of valid address range "&lt;/P&gt;&lt;P&gt;is because WDOG1 should not be in dcd data,&lt;/P&gt;&lt;P&gt;please remove this line ("setmem /16&amp;nbsp;&amp;nbsp;&amp;nbsp; 0x020bc000 =&amp;nbsp;&amp;nbsp;&amp;nbsp; 0x30" in *.inc file).&lt;/P&gt;&lt;P&gt;Valid dcd data addresses are given in&lt;/P&gt;&lt;P&gt;Table 8-29. Valid DCD Address Ranges &lt;A href="http://cache.freescale.com/files/32bit/doc/ref_manual/IMX6SLRM.pdf?fasp=1&amp;amp;WT_TYPE=Reference%20Manuals&amp;amp;WT_VENDOR=FREESCALE&amp;amp;WT_FILE_FORMAT=pdf&amp;amp;WT_ASSET=Documentation&amp;amp;fileExt=.pdf"&gt;IMX6SLRM&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;&lt;P&gt;igor&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 05 Feb 2015 09:29:16 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/LPDDR2-config-on-imx6sl/m-p/348774#M48322</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2015-02-05T09:29:16Z</dc:date>
    </item>
    <item>
      <title>Re: LPDDR2 config on imx6sl</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/LPDDR2-config-on-imx6sl/m-p/348775#M48323</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi igor&lt;/P&gt;&lt;P&gt;I have tried what you said,the result is &lt;/P&gt;&lt;P&gt;HAB_TYPE: DEVELOP&lt;/P&gt;&lt;P&gt;rom_write: reading HAB ack failed 0x00000000&lt;/P&gt;&lt;P&gt;ROM Write failed, addr: 0x021b001c&lt;/P&gt;&lt;P&gt;Write dcd failed.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;and I know MMDC valid addr start from 0x021B0000,but your Aid can automatically generate the Inc, I cannot motify it because I dont know whether it is right after motifying it.&lt;/P&gt;&lt;P&gt;So could you give me another help? 3q very much!&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 05 Feb 2015 10:16:12 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/LPDDR2-config-on-imx6sl/m-p/348775#M48323</guid>
      <dc:creator>tony_l_cai</dc:creator>
      <dc:date>2015-02-05T10:16:12Z</dc:date>
    </item>
    <item>
      <title>Re: LPDDR2 config on imx6sl</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/LPDDR2-config-on-imx6sl/m-p/348776#M48324</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi tony&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;you can try board SDK (one can run it with jtag) with your ddr settings&lt;/P&gt;&lt;P&gt;and use ddr_test.c (there one can find MX6SL_EVK_LPDDR2_v0.9.inc)&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;A href="http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=i.MX6Q&amp;amp;nodeId=018rH3ZrDRB24A&amp;amp;fpsp=1&amp;amp;tab=Design_Tools_Tab"&gt;i.MX 6Series Platform SDK&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;after these simple tests will run OK, one can try DDR test&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;~igor&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 05 Feb 2015 11:59:00 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/LPDDR2-config-on-imx6sl/m-p/348776#M48324</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2015-02-05T11:59:00Z</dc:date>
    </item>
    <item>
      <title>Re: LPDDR2 config on imx6sl</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/LPDDR2-config-on-imx6sl/m-p/348777#M48325</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;SPAN style="color: #3d3d3d; font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif;"&gt;Hi Igor,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #3d3d3d; font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif;"&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #3d3d3d; font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; We just have Trace32 in our hands. Can you tell us how to use this SDK with Trace32 or the method to debug this issue with Trace32?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #3d3d3d; font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif;"&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #3d3d3d; font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif;"&gt;Thanks&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #3d3d3d; font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif;"&gt;Tony&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 06 Feb 2015 00:53:35 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/LPDDR2-config-on-imx6sl/m-p/348777#M48325</guid>
      <dc:creator>tony_l_cai</dc:creator>
      <dc:date>2015-02-06T00:53:35Z</dc:date>
    </item>
    <item>
      <title>Re: LPDDR2 config on imx6sl</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/LPDDR2-config-on-imx6sl/m-p/348778#M48326</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi tony&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;in SDK you will find ../tools/lauterbach&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;~igor&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 06 Feb 2015 01:36:47 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/LPDDR2-config-on-imx6sl/m-p/348778#M48326</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2015-02-06T01:36:47Z</dc:date>
    </item>
    <item>
      <title>Re: LPDDR2 config on imx6sl</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/LPDDR2-config-on-imx6sl/m-p/348779#M48327</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;Tony,&lt;BR /&gt;&lt;BR /&gt;&amp;nbsp; I was mistaken with DRAM part number, sorry.&lt;BR /&gt;In the same time, in Your file “clipboard.png” number of CS = 2 ; this means &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;at least two DRAM devices. Please correct it (number of CS).&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;Regards, &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;Yuri.&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 06 Feb 2015 05:18:22 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/LPDDR2-config-on-imx6sl/m-p/348779#M48327</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2015-02-06T05:18:22Z</dc:date>
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