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    <title>i.MX Processors中的主题 i.MX53 Reference Manual Errors, is there a list?</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/i-MX53-Reference-Manual-Errors-is-there-a-list/m-p/348283#M48246</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I'm going through the Reference Manual and finding a lot of obvious errors (apart from the spelling errors).&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;There doesn't seem to be an Errata or update to this manual.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Is anyone keeping a list of errors, because Freescale doesn't seem to be doing this.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Is there a "place" of some sort on this site where this sort of document could be created, indexed and more importantly FOUND by others using this manual?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Here are ones I've found in the following document over the course of a few days trying to track down a DDR3 memory problem that happens at high and low temperatures.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;i.MX53 Multimedia Applications Processor Reference Manual&lt;/P&gt;&lt;P&gt;Document Number: iMX53RM&lt;/P&gt;&lt;P&gt;Rev. 2.1, 06/2012&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Table 43-2. DDR Output Driver Average Impedance&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; DDR3 mode - Calibration resistance = 200&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; This doesn't match:&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; 43.3.454 IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; NVCC_EMI_DRAM=1.5V+/-5% (DDR3), ddr_sel='00': 240 Ohm&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Table 43-2. DDR Output Driver Average Impedance&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; DDR3 mode: Hi-Z4, 240, 120, 80, 60, 48, 48, 34.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; The resistance values listed for "5" and "6" are the same.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; I have measured the resistances on the DDR_RESET pin as&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; approximately "246, 108, 71, 53, 43, 35, 30" indicating&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; that the duplicates in the table are a a mistake. The&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; equivalent tables in the i.MX6 manuals give 240, 120,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; 80, 60, 48, 40 and 34 ohms.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;43.3.343 IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3&lt;/P&gt;&lt;P&gt;43.3.347 IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2&lt;/P&gt;&lt;P&gt;43.3.352 IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0&lt;/P&gt;&lt;P&gt;43.3.357 IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; Both the Diagram and Table state that the 22:24 field is&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; "Reserved and Read Only" when it has to be written with&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; the ODT value, as these pins are I/O (as are the data pins).&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; Checking the registers in the debugger shows these bits to be&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; read/write and the Freescale sample code sets these bits.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; The Diagram also shows the Reset state as "1" wuile the&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; Description shows it as "0".&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;43.3.353 IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0&lt;/P&gt;&lt;P&gt;43.3.346 IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; The SDODT0 register diagram has the ODT field read/write whereas&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; the description has it read-only, and the register is read-only.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; The SDODT1 section is correct.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;43.3.344 IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1&lt;/P&gt;&lt;P&gt;43.3.356 IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; The register diagram has the DSE field read/write whereas the&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; description has it read-only, and the register is read-only.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;43.3.359 IOMUXC_SW_PAD_CTL_PAD_PMIC_ON_REQ&lt;/P&gt;&lt;P&gt;43.3.360 IOMUXC_SW_PAD_CTL_PAD_PMIC_STBY_REQ&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; The Register Diagram gives the Reset State of the DSE_TEST and PUE&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; bits as "1" while the description has them as "0". The "Strength Mode"&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; bit is the reverse,"0" in the Diagram and "1" in the Description.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;43.3.358 IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; The Diagram shows the PUE reset value of "1" and the PUS reset&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; value of "00" whereas the text shows PUS as "0" and PUS as "10".&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; The DQM0, DQM2 and DQM3 sections are correct.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;43.3.278 IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; The Diagram gives DSE and SRE as read-only while the Description&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; has them as read-write.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;43.3.351 IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; The Diagram gives PKE, PUE and PUS as read-write whereas the&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; Description has them as read-only. The SDCLK_1 section is OK.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;In Addemdum 2:&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Table 2-10. Common Fusemap&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; Address 0C00 is shown to be in Bank 0 when it is in Bank 1. This&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; is correct in section 2.2.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;2.2 Fusemap Description Table&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; Addresses 1814, 1818 and 181C are shown to be in Bank 0. This&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; is correct in Table 2-10.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Tom&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Sun, 10 Aug 2014 02:38:23 GMT</pubDate>
    <dc:creator>TomE</dc:creator>
    <dc:date>2014-08-10T02:38:23Z</dc:date>
    <item>
      <title>i.MX53 Reference Manual Errors, is there a list?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX53-Reference-Manual-Errors-is-there-a-list/m-p/348283#M48246</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I'm going through the Reference Manual and finding a lot of obvious errors (apart from the spelling errors).&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;There doesn't seem to be an Errata or update to this manual.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Is anyone keeping a list of errors, because Freescale doesn't seem to be doing this.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Is there a "place" of some sort on this site where this sort of document could be created, indexed and more importantly FOUND by others using this manual?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Here are ones I've found in the following document over the course of a few days trying to track down a DDR3 memory problem that happens at high and low temperatures.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;i.MX53 Multimedia Applications Processor Reference Manual&lt;/P&gt;&lt;P&gt;Document Number: iMX53RM&lt;/P&gt;&lt;P&gt;Rev. 2.1, 06/2012&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Table 43-2. DDR Output Driver Average Impedance&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; DDR3 mode - Calibration resistance = 200&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; This doesn't match:&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; 43.3.454 IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; NVCC_EMI_DRAM=1.5V+/-5% (DDR3), ddr_sel='00': 240 Ohm&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Table 43-2. DDR Output Driver Average Impedance&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; DDR3 mode: Hi-Z4, 240, 120, 80, 60, 48, 48, 34.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; The resistance values listed for "5" and "6" are the same.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; I have measured the resistances on the DDR_RESET pin as&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; approximately "246, 108, 71, 53, 43, 35, 30" indicating&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; that the duplicates in the table are a a mistake. The&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; equivalent tables in the i.MX6 manuals give 240, 120,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; 80, 60, 48, 40 and 34 ohms.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;43.3.343 IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3&lt;/P&gt;&lt;P&gt;43.3.347 IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2&lt;/P&gt;&lt;P&gt;43.3.352 IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0&lt;/P&gt;&lt;P&gt;43.3.357 IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; Both the Diagram and Table state that the 22:24 field is&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; "Reserved and Read Only" when it has to be written with&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; the ODT value, as these pins are I/O (as are the data pins).&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; Checking the registers in the debugger shows these bits to be&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; read/write and the Freescale sample code sets these bits.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; The Diagram also shows the Reset state as "1" wuile the&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; Description shows it as "0".&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;43.3.353 IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0&lt;/P&gt;&lt;P&gt;43.3.346 IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; The SDODT0 register diagram has the ODT field read/write whereas&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; the description has it read-only, and the register is read-only.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; The SDODT1 section is correct.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;43.3.344 IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1&lt;/P&gt;&lt;P&gt;43.3.356 IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; The register diagram has the DSE field read/write whereas the&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; description has it read-only, and the register is read-only.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;43.3.359 IOMUXC_SW_PAD_CTL_PAD_PMIC_ON_REQ&lt;/P&gt;&lt;P&gt;43.3.360 IOMUXC_SW_PAD_CTL_PAD_PMIC_STBY_REQ&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; The Register Diagram gives the Reset State of the DSE_TEST and PUE&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; bits as "1" while the description has them as "0". The "Strength Mode"&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; bit is the reverse,"0" in the Diagram and "1" in the Description.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;43.3.358 IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; The Diagram shows the PUE reset value of "1" and the PUS reset&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; value of "00" whereas the text shows PUS as "0" and PUS as "10".&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; The DQM0, DQM2 and DQM3 sections are correct.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;43.3.278 IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; The Diagram gives DSE and SRE as read-only while the Description&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; has them as read-write.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;43.3.351 IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; The Diagram gives PKE, PUE and PUS as read-write whereas the&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; Description has them as read-only. The SDCLK_1 section is OK.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;In Addemdum 2:&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Table 2-10. Common Fusemap&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; Address 0C00 is shown to be in Bank 0 when it is in Bank 1. This&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; is correct in section 2.2.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;2.2 Fusemap Description Table&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; Addresses 1814, 1818 and 181C are shown to be in Bank 0. This&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; is correct in Table 2-10.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Tom&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sun, 10 Aug 2014 02:38:23 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX53-Reference-Manual-Errors-is-there-a-list/m-p/348283#M48246</guid>
      <dc:creator>TomE</dc:creator>
      <dc:date>2014-08-10T02:38:23Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX53 Reference Manual Errors, is there a list?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX53-Reference-Manual-Errors-is-there-a-list/m-p/348284#M48247</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;It is true that documentation can sometimes hold&amp;nbsp; several errors and Freescale does work on updating documentation constantly. As you see the Reference Manual is now on revision 2.1 and there is still work to be done!&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I’m double checking and escalating these observations so they are considered for the next revision of the document. Please note that it might take some time for changes to be reflected on a new release.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;There is no central repository for this feedback as it’s intended to be finally reflected on the official document but your input in our communities will very likely serve other users to be aware of these errors and we’re taking notes on them.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 10pt; font-family: arial,helvetica,sans-serif;"&gt;Thank you for taking the time to documenting these errors and pointing them out!&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 12 Aug 2014 20:44:02 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX53-Reference-Manual-Errors-is-there-a-list/m-p/348284#M48247</guid>
      <dc:creator>gusarambula</dc:creator>
      <dc:date>2014-08-12T20:44:02Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX53 Reference Manual Errors, is there a list?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX53-Reference-Manual-Errors-is-there-a-list/m-p/348285#M48248</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&amp;gt; I’m double checking and escalating these observations so they are considered for the next revision of the document.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thank you for that.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;gt; Freescale does work on updating documentation constantly.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;But this manual is so old (June 2012) that from previous experience I wasn't expecting any further revisions or addenda.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;gt; There is no central repository for this feedback&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Freescale use to have a Ticket System for this, but that has been closed down.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Do you have any idea why these manuals have these spelling errors in them? A run over with a spelling checker should be easy to do. Maybe you have a "company technical dictionary" and these mis-spellings have accidentally been added to it, that's happened before. The number of obvious spelling errors lowers confidence in the technical content when all these have slipped through the checking. I listed a few of them here:&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.nxp.com/message/425415"&gt;i.MX53 &amp;amp;amp; i.MX6 Reference Manual Spelling Problems&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;My favourites are "CSU &lt;SPAN style="text-decoration: underline;"&gt;manges&lt;/SPAN&gt; system &lt;SPAN style="text-decoration: underline;"&gt;sucurity&lt;/SPAN&gt; alarms", "&lt;SPAN style="text-decoration: underline;"&gt;writting&lt;/SPAN&gt;, &lt;SPAN style="text-decoration: underline;"&gt;wrotten&lt;/SPAN&gt;, &lt;SPAN style="text-decoration: underline;"&gt;wrutten&lt;/SPAN&gt;", "&lt;SPAN style="text-decoration: underline;"&gt;regitsers&lt;/SPAN&gt;, &lt;SPAN style="text-decoration: underline;"&gt;regitsters&lt;/SPAN&gt;, &lt;SPAN style="text-decoration: underline;"&gt;regsier&lt;/SPAN&gt;, &lt;SPAN style="text-decoration: underline;"&gt;regsiter&lt;/SPAN&gt;, &lt;SPAN style="text-decoration: underline;"&gt;regsiters&lt;/SPAN&gt;", "&lt;SPAN style="text-decoration: underline;"&gt;cannnot&lt;/SPAN&gt;" and most ironically, "&lt;SPAN style="text-decoration: underline;"&gt;&lt;STRONG&gt;accruate&lt;/STRONG&gt;&lt;/SPAN&gt;".&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Tom&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 13 Aug 2014 08:05:39 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX53-Reference-Manual-Errors-is-there-a-list/m-p/348285#M48248</guid>
      <dc:creator>TomE</dc:creator>
      <dc:date>2014-08-13T08:05:39Z</dc:date>
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