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    <title>topic Re: SabreSD: PCIe Endpoint in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/SabreSD-PCIe-Endpoint/m-p/346670#M47907</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Farhan&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;does it work with internal reference with PC RC ?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;&lt;P&gt;igor&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Sat, 25 Oct 2014 11:15:16 GMT</pubDate>
    <dc:creator>igorpadykov</dc:creator>
    <dc:date>2014-10-25T11:15:16Z</dc:date>
    <item>
      <title>SabreSD: PCIe Endpoint</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/SabreSD-PCIe-Endpoint/m-p/346669#M47906</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I am trying to connect SabreSD as an endpoint to a PC. I followed &lt;A href="https://community.nxp.com/docs/DOC-95014"&gt;i.MX6Q PCIe EP/RC Validation System&lt;/A&gt; and &lt;A href="https://community.nxp.com/thread/304283"&gt;i.MX6Q: Using an external reference for PCIe&lt;/A&gt; for building the kernel image. I set clkdiv2 and mpll to accept 100Mhz external clock.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;when I connect it with a PC, PC says PCIe link initialization failed. With internal reference, EP works fine with a Sabrelite RC. Please help!!!&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 23 Oct 2014 10:04:55 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/SabreSD-PCIe-Endpoint/m-p/346669#M47906</guid>
      <dc:creator>farhanmasood</dc:creator>
      <dc:date>2014-10-23T10:04:55Z</dc:date>
    </item>
    <item>
      <title>Re: SabreSD: PCIe Endpoint</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/SabreSD-PCIe-Endpoint/m-p/346670#M47907</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Farhan&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;does it work with internal reference with PC RC ?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;&lt;P&gt;igor&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sat, 25 Oct 2014 11:15:16 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/SabreSD-PCIe-Endpoint/m-p/346670#M47907</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2014-10-25T11:15:16Z</dc:date>
    </item>
    <item>
      <title>Re: SabreSD: PCIe Endpoint</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/SabreSD-PCIe-Endpoint/m-p/346671#M47908</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;no it doesnt :smileysad:&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 27 Oct 2014 06:29:43 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/SabreSD-PCIe-Endpoint/m-p/346671#M47908</guid>
      <dc:creator>farhanmasood</dc:creator>
      <dc:date>2014-10-27T06:29:43Z</dc:date>
    </item>
    <item>
      <title>Re: SabreSD: PCIe Endpoint</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/SabreSD-PCIe-Endpoint/m-p/346672#M47909</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Farhan&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;suggest to check if TX lines on PC side have in series 0.1uF capacitors as C6,C5&lt;/P&gt;&lt;P&gt;in SPF-27392 p.16&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;A href="http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=RDIMX6SABREPLAT"&gt;SABRE Platform for Smart Devices Reference Design Based on the i.MX 6 Series&amp;nbsp; &lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;~igor&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 27 Oct 2014 07:43:05 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/SabreSD-PCIe-Endpoint/m-p/346672#M47909</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2014-10-27T07:43:05Z</dc:date>
    </item>
    <item>
      <title>Re: SabreSD: PCIe Endpoint</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/SabreSD-PCIe-Endpoint/m-p/346673#M47910</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Yes there are caps on both Tx lines. None on Rx lines.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 27 Oct 2014 10:04:42 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/SabreSD-PCIe-Endpoint/m-p/346673#M47910</guid>
      <dc:creator>farhanmasood</dc:creator>
      <dc:date>2014-10-27T10:04:42Z</dc:date>
    </item>
    <item>
      <title>Re: SabreSD: PCIe Endpoint</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/SabreSD-PCIe-Endpoint/m-p/346674#M47911</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I think you can try several PCs, seems noise (more on PC&lt;/P&gt;&lt;P&gt;than on i.MX6 RC board) greatly affects connection.&lt;/P&gt;&lt;P&gt;You can check posts from key two with SABRE Lite board,&lt;/P&gt;&lt;P&gt;checking link with ./memtool -32 01ffc72c and trying different cables&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.nxp.com/docs/DOC-95014"&gt;i.MX6Q PCIe EP/RC Validation System&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;~igor&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 27 Oct 2014 14:09:59 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/SabreSD-PCIe-Endpoint/m-p/346674#M47911</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2014-10-27T14:09:59Z</dc:date>
    </item>
    <item>
      <title>Re: SabreSD: PCIe Endpoint</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/SabreSD-PCIe-Endpoint/m-p/346675#M47912</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I would suggest you should make sure the external clock can work correctly firstly, then tried it with PC.&amp;nbsp; &lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 19 Nov 2014 02:43:57 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/SabreSD-PCIe-Endpoint/m-p/346675#M47912</guid>
      <dc:creator>b47504</dc:creator>
      <dc:date>2014-11-19T02:43:57Z</dc:date>
    </item>
    <item>
      <title>This an automatic process.  We are marking this post as s...</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/SabreSD-PCIe-Endpoint/m-p/1135982#M161129</link>
      <description>&lt;B&gt;This an automatic process.&lt;/B&gt;&lt;BR /&gt;&lt;BR /&gt;
We are marking this post as solved, due to the either low activity or any reply marked as correct.&lt;BR /&gt;&lt;BR /&gt;
If you have additional questions, please create a new post and reference to this closed post.&lt;BR /&gt;&lt;BR /&gt;
NXP Community!</description>
      <pubDate>Thu, 03 Sep 2020 15:03:42 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/SabreSD-PCIe-Endpoint/m-p/1135982#M161129</guid>
      <dc:creator>CommunityBot</dc:creator>
      <dc:date>2020-09-03T15:03:42Z</dc:date>
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