ECSPI Read and Write Timings

philippechapet — Wed, 22 Oct 2014 14:53:37 GMT

Dear,

On this document, en page 77:

http://cache.freescale.com/files/32bit/doc/data_sheet/IMX6SDLAEC.pdf?fasp=1

The tclk timings are 43ns for Read and 15ns for Write.

However the ECSPI is a shift registry. So for each clk, there is a read and a write.

So what is the difference between "ECSPIx_SCLK Cycle Time–Read" and "ECSPIx_SCLK Cycle Time–Write" ?

Best regards

Philippe

Re: ECSPI Read and Write Timings

Yuri — Thu, 23 Oct 2014 02:43:25 GMT

The hardware specs of i.MX6 Datasheet(s) regarding eCSPI timings are results

of tests. Requirements for reliable read are more strict than for writing. One of SPI
ideas is simultaneous read and write ops (implemented as a common shift register),

but there are devices that support SPI interface, but do not need both read and write
ops. To say roughly we can use "slow" ADC and "fast" DAC.

Have a great day,
Yuri

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i.MX ProcessorsのトピックECSPI Read and Write Timings

ECSPI Read and Write Timings

Re: ECSPI Read and Write Timings