<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Voltage power up sequence in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Voltage-power-up-sequence/m-p/344012#M47376</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;What is the proper voltage power up sequence for MX6SoloX CPU?&lt;/P&gt;&lt;P&gt;As stated in datasheet, VDD_HIGH and VDD_SNVS can be powered up simuntaneously. What about other voltages then, especially core voltage and 3.3V IO.&lt;/P&gt;&lt;P&gt;Can everything be powered up at the same time?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 24 Mar 2015 08:33:01 GMT</pubDate>
    <dc:creator>marijanvesligaj</dc:creator>
    <dc:date>2015-03-24T08:33:01Z</dc:date>
    <item>
      <title>Voltage power up sequence</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Voltage-power-up-sequence/m-p/344012#M47376</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;What is the proper voltage power up sequence for MX6SoloX CPU?&lt;/P&gt;&lt;P&gt;As stated in datasheet, VDD_HIGH and VDD_SNVS can be powered up simuntaneously. What about other voltages then, especially core voltage and 3.3V IO.&lt;/P&gt;&lt;P&gt;Can everything be powered up at the same time?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 24 Mar 2015 08:33:01 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Voltage-power-up-sequence/m-p/344012#M47376</guid>
      <dc:creator>marijanvesligaj</dc:creator>
      <dc:date>2015-03-24T08:33:01Z</dc:date>
    </item>
    <item>
      <title>Re: Voltage power up sequence</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Voltage-power-up-sequence/m-p/344013#M47377</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Marijan&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;everything can not be powered up at the same time,&lt;/P&gt;&lt;P&gt;datasheet also describes restrictions for VDD_ARM_IN and VDD_SOC_IN&lt;/P&gt;&lt;P&gt;in case external POR. In general recommended to follow i.MX6SX SDB deisgn&lt;/P&gt;&lt;P&gt;(with MMPF0100F6)&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;A href="http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=RDIMX6SABREBRD&amp;amp;fpsp=1&amp;amp;tab=Design_Tools_Tab"&gt;IMX6SOLOX-SABRESDB-DESIGNFILES&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;&lt;P&gt;igor&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;P&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 25 Mar 2015 01:10:35 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Voltage-power-up-sequence/m-p/344013#M47377</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2015-03-25T01:10:35Z</dc:date>
    </item>
  </channel>
</rss>

