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    <title>topic MMU page table location in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/MMU-page-table-location/m-p/342559#M47085</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I've noticed that in the Freescale bare metal SDK, the MMU's page table is located in the first 16k of OCRAM starting at 0x900000.&amp;nbsp; If you look at the processor reference manual for IMX6D/Q however, in figure 8.3 it shows the MMU table starting at 0x938000.&amp;nbsp; Obviously the SDK works so it seems like the manual is wrong, but I'd like to get clarification on this.&amp;nbsp; Thanks!&amp;nbsp; &lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Fri, 27 Feb 2015 00:00:03 GMT</pubDate>
    <dc:creator>elijahbrown</dc:creator>
    <dc:date>2015-02-27T00:00:03Z</dc:date>
    <item>
      <title>MMU page table location</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/MMU-page-table-location/m-p/342559#M47085</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I've noticed that in the Freescale bare metal SDK, the MMU's page table is located in the first 16k of OCRAM starting at 0x900000.&amp;nbsp; If you look at the processor reference manual for IMX6D/Q however, in figure 8.3 it shows the MMU table starting at 0x938000.&amp;nbsp; Obviously the SDK works so it seems like the manual is wrong, but I'd like to get clarification on this.&amp;nbsp; Thanks!&amp;nbsp; &lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 27 Feb 2015 00:00:03 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/MMU-page-table-location/m-p/342559#M47085</guid>
      <dc:creator>elijahbrown</dc:creator>
      <dc:date>2015-02-27T00:00:03Z</dc:date>
    </item>
    <item>
      <title>Re: MMU page table location</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/MMU-page-table-location/m-p/342560#M47086</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Elijah&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;for i.MX6QD OCRAM range is 0x900000-0x93FFFF,&lt;/P&gt;&lt;P&gt;MMU can be assigned to any address, this depends on application.&lt;/P&gt;&lt;P&gt;iROM use one ranges, SDK other, Linux may have another choices.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;&lt;P&gt;igor&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;P&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 27 Feb 2015 01:17:25 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/MMU-page-table-location/m-p/342560#M47086</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2015-02-27T01:17:25Z</dc:date>
    </item>
    <item>
      <title>Re: MMU page table location</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/MMU-page-table-location/m-p/342561#M47087</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Ok I see, I missed the line where it writes the address to TTBR0.&amp;nbsp; Thanks.&amp;nbsp; &lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 27 Feb 2015 01:39:58 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/MMU-page-table-location/m-p/342561#M47087</guid>
      <dc:creator>elijahbrown</dc:creator>
      <dc:date>2015-02-27T01:39:58Z</dc:date>
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