i.MX6DL:Inbound address setting behavior (PCIE_PL_iATUVR)

koichisakagami — Wed, 10 Dec 2014 10:09:51 GMT

Dear community,

We have been developing their product with iMX6DualLite.
We make the device driver for PCIexpress.

In the case of setting to the PCIE_PL_iATURLBA register for Inbound iATU address value,
we execute the following sequence.

1.set to the Viewport Register (PCIE_PL_iATUVR).
2.set to the iATU Region Lower Base Address Register(PCIE_PL_iATURLBA) .
3.set to the Viewport Register (PCIE_PL_iATUVR) another value.

It is the "No3" timing that the address setting written in (PCIE_PL_iATURLBA)
is reflected by actual behavior.
It is NOT "No2" timing.

[Question]
Is above behavior the iATU specification ?

Meantime,
in the case of setting to the PCIE_PL_iATURLBA register for "Outbound" iATU address value,
it is the "No2" timing that the address setting written in (PCIE_PL_iATURLBA)
is reflected by actual behavior.

Best Regards,
Koichi Sakagami

Re: i.MX6DL:Inbound address setting behavior (PCIE_PL_iATUVR)

Yuri — Wed, 17 Dec 2014 09:06:54 GMT

You may use as an example the C-function pcie_map_space() in
iMX6_Platform_SDK/sdk/drivers/pcie/src/pcie.c

HW_PCIE_PL_IATUVR_WR((viewport & 0x0F) | (0 << 31));

HW_PCIE_PL_IATURLBA_WR(addr_base_cpu_side);

HW_PCIE_PL_IATURUBA_WR(0);

HW_PCIE_PL_IATURLA_WR(addr_base_cpu_side + size - 1);

HW_PCIE_PL_IATURUTA_WR(0);

HW_PCIE_PL_IATURLTA_WR(addr_base_pcie_side);

HW_PCIE_PL_IATURC1_WR(tlp_type & 0x0F);

HW_PCIE_PL_IATURC2_WR(((unsigned int)(1 << 31)));

Below is SDK link :

https://www.freescale.com/webapp/Download?colCode=i.MX6_PLATFORM_SDK&location=null

Summary page :

< http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=i.MX6Q&fpsp=1&tab=Design_Tools_Tab

Have a great day,
Yuri

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topic Re: i.MX6DL:Inbound address setting behavior (PCIE_PL_iATUVR) in i.MX Processors

i.MX6DL:Inbound address setting behavior (PCIE_PL_iATUVR)

Re: i.MX6DL:Inbound address setting behavior (PCIE_PL_iATUVR)