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    <title>topic i.MX6DL:iATU register write sequence in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6DL-iATU-register-write-sequence/m-p/339166#M46344</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Dear community,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;We have been developing their product with iMX6DualLite.&lt;BR /&gt;We make the device driver for PCIexpress.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;In i.MX6 Reference Manual ( MX6SDLRM ) 4443 page,&lt;BR /&gt;it says that " Since AXI core is async to the core_clk, the iATU registers&lt;BR /&gt;may not be updated while operations are in progress on the AXI&lt;BR /&gt;Bridge Slave interface. "&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;[Question]&lt;BR /&gt;In the case of writing to the PCIE_PL_iATURLBA register,&lt;BR /&gt;Is it the correct method as follows ?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;1. write to the Viewport Register (PCIE_PL_iATUVR).&lt;BR /&gt;2. read the Viewport Register (PCIE_PL_iATUVR).&lt;BR /&gt;3. if the correct value is read, write to the PCIE_PL_iATURLBA register.&lt;BR /&gt;4. if the correct value is NOT read, wait until the correct value is read.&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; And write to the PCIE_PL_iATURLBA register.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best Regards,&lt;BR /&gt;Koichi Sakagami&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 10 Dec 2014 10:06:23 GMT</pubDate>
    <dc:creator>koichisakagami</dc:creator>
    <dc:date>2014-12-10T10:06:23Z</dc:date>
    <item>
      <title>i.MX6DL:iATU register write sequence</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6DL-iATU-register-write-sequence/m-p/339166#M46344</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Dear community,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;We have been developing their product with iMX6DualLite.&lt;BR /&gt;We make the device driver for PCIexpress.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;In i.MX6 Reference Manual ( MX6SDLRM ) 4443 page,&lt;BR /&gt;it says that " Since AXI core is async to the core_clk, the iATU registers&lt;BR /&gt;may not be updated while operations are in progress on the AXI&lt;BR /&gt;Bridge Slave interface. "&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;[Question]&lt;BR /&gt;In the case of writing to the PCIE_PL_iATURLBA register,&lt;BR /&gt;Is it the correct method as follows ?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;1. write to the Viewport Register (PCIE_PL_iATUVR).&lt;BR /&gt;2. read the Viewport Register (PCIE_PL_iATUVR).&lt;BR /&gt;3. if the correct value is read, write to the PCIE_PL_iATURLBA register.&lt;BR /&gt;4. if the correct value is NOT read, wait until the correct value is read.&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; And write to the PCIE_PL_iATURLBA register.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best Regards,&lt;BR /&gt;Koichi Sakagami&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 10 Dec 2014 10:06:23 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6DL-iATU-register-write-sequence/m-p/339166#M46344</guid>
      <dc:creator>koichisakagami</dc:creator>
      <dc:date>2014-12-10T10:06:23Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX6DL:iATU register write sequence</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6DL-iATU-register-write-sequence/m-p/339167#M46345</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&amp;nbsp; Please look at the next thread for recommended sequence.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;"i.MX6DL:Inbound address setting behavior (PCIE_PL_iATUVR)"&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;A class="jive-link-thread-small" data-containerid="2004" data-containertype="14" data-objectid="336840" data-objecttype="1" href="https://community.freescale.com/thread/336840"&gt;https://community.freescale.com/thread/336840&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Have a great day,&lt;BR /&gt;Yuri&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 17 Dec 2014 09:12:12 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6DL-iATU-register-write-sequence/m-p/339167#M46345</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2014-12-17T09:12:12Z</dc:date>
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