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    <title>topic Re: Configuring i.MX6 as endpoint memory device in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Configuring-i-MX6-as-endpoint-memory-device/m-p/338660#M46269</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Please check the attached patch and following test steps.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Test steps and results:&lt;/P&gt;&lt;P&gt;First of all, Enable CONFIG_PCI_MSI=y, and rebuild the image&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Then,&lt;/P&gt;&lt;P&gt;EP side(console command and kernel message):&lt;/P&gt;&lt;P&gt;&lt;A class="jive-link-email-small" data-content-finding="Community" href="mailto:root@sabresd_6dq:/"&gt;root@sabresd_6dq:/&lt;/A&gt; # memtool 1ff8000=1&lt;BR /&gt;Writing 32-bit value 0x1 to address 0x01FF8000&lt;BR /&gt;&lt;A class="jive-link-email-small" data-content-finding="Community" href="mailto:root@sabresd_6dq:/"&gt;root@sabresd_6dq:/&lt;/A&gt; #&lt;/P&gt;&lt;P&gt;|&lt;BR /&gt;|&lt;BR /&gt;\/&lt;/P&gt;&lt;P&gt;RC side(console command and kernel message):&lt;/P&gt;&lt;P&gt;&lt;A class="jive-link-email-small" data-content-finding="Community" href="mailto:root@sabresd_6dq:/"&gt;root@sabresd_6dq:/&lt;/A&gt; #&lt;BR /&gt;Test for MSI interrupt - handle_simple_irq triggered by irq: 497&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;A class="jive-link-email-small" data-content-finding="Community" href="mailto:root@sabresd_6dq:/"&gt;root@sabresd_6dq:/&lt;/A&gt; # cat /proc/interrupts | grep MSI&lt;BR /&gt;497:&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 1&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0&amp;nbsp; PCIe-MSI&lt;BR /&gt;&lt;A class="jive-link-email-small" data-content-finding="Community" href="mailto:root@sabresd_6dq:/"&gt;root@sabresd_6dq:/&lt;/A&gt; #&lt;/P&gt;&lt;P&gt;|&lt;BR /&gt;|&lt;BR /&gt;\/&lt;/P&gt;&lt;P&gt;EP side(console command and kernel message):&lt;/P&gt;&lt;P&gt;&lt;A class="jive-link-email-small" data-content-finding="Community" href="mailto:root@sabresd_6dq:/"&gt;root@sabresd_6dq:/&lt;/A&gt; # memtool 1ff8000=1&lt;BR /&gt;Writing 32-bit value 0x1 to address 0x01FF8000&lt;/P&gt;&lt;P&gt;|&lt;BR /&gt;|&lt;BR /&gt;\/&lt;/P&gt;&lt;P&gt;RC side(console command and kernel message):&lt;/P&gt;&lt;P&gt;&lt;A class="jive-link-email-small" data-content-finding="Community" href="mailto:root@sabresd_6dq:/"&gt;root@sabresd_6dq:/&lt;/A&gt; #&lt;BR /&gt;Test for MSI interrupt - handle_simple_irq triggered by irq: 497&lt;/P&gt;&lt;P&gt;&lt;A class="jive-link-email-small" data-content-finding="Community" href="mailto:root@sabresd_6dq:/"&gt;root@sabresd_6dq:/&lt;/A&gt; # cat /proc/interrupts | grep MSI&lt;BR /&gt;497:&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 2&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0&amp;nbsp; PCIe-MSI&lt;BR /&gt;&lt;A class="jive-link-email-small" data-content-finding="Community" href="mailto:root@sabresd_6dq:/"&gt;root@sabresd_6dq:/&lt;/A&gt; #&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Have a great day,&lt;BR /&gt;Jaime&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Mon, 08 Sep 2014 15:09:41 GMT</pubDate>
    <dc:creator>jamesbone</dc:creator>
    <dc:date>2014-09-08T15:09:41Z</dc:date>
    <item>
      <title>Configuring i.MX6 as endpoint memory device</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Configuring-i-MX6-as-endpoint-memory-device/m-p/338659#M46268</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;I am new to pcie and imx6.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I am trying to configure configure BD-SL-i.MX6 as endpoint memory device. I have gone through the &lt;A href="https://community.nxp.com/docs/DOC-95014"&gt;i.MX6Q PCIe EP/RC Validation System&lt;/A&gt;. &lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: Arial, sans-serif; font-size: 10pt; line-height: 1.5em;"&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: Arial, sans-serif; font-size: 10pt; line-height: 1.5em;"&gt;In this patch&amp;nbsp; bars are setup under the &lt;/SPAN&gt;&lt;EM style="font-family: Arial, sans-serif; font-size: 10pt; line-height: 1.5em;"&gt;imx_pcie_regions_setup() &lt;/EM&gt;&lt;SPAN style="font-family: Arial, sans-serif; font-size: 10pt; line-height: 1.5em;"&gt;but I could not locate any inbound setup in case root complex tried to access the ep memory. Is that required?.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: Arial, sans-serif; font-size: 10pt; line-height: 1.5em;"&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: Arial, sans-serif; font-size: 10pt; line-height: 1.5em;"&gt;It also did not allocate memory space from the ram to these memory space. Please let me know if I am missing any thing.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: Arial, sans-serif; font-size: 10pt; line-height: 1.5em;"&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: Arial, sans-serif; font-size: 10pt; line-height: 1.5em;"&gt;Also can we map more than the 16mb space?. Like I want to configure endpoint whole ram accessible to root complex.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: Arial, sans-serif; font-size: 10pt; line-height: 1.5em;"&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: Arial, sans-serif; font-size: 10pt; line-height: 1.5em;"&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;Thanks,&lt;/P&gt;&lt;P&gt;Haider&lt;/P&gt;&lt;H3 style="font-family: 'Open Sans', sans-serif; color: #222222; text-align: center; background-position: initial;"&gt;&lt;/H3&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 04 Sep 2014 08:07:18 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Configuring-i-MX6-as-endpoint-memory-device/m-p/338659#M46268</guid>
      <dc:creator>haider</dc:creator>
      <dc:date>2014-09-04T08:07:18Z</dc:date>
    </item>
    <item>
      <title>Re: Configuring i.MX6 as endpoint memory device</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Configuring-i-MX6-as-endpoint-memory-device/m-p/338660#M46269</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Please check the attached patch and following test steps.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Test steps and results:&lt;/P&gt;&lt;P&gt;First of all, Enable CONFIG_PCI_MSI=y, and rebuild the image&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Then,&lt;/P&gt;&lt;P&gt;EP side(console command and kernel message):&lt;/P&gt;&lt;P&gt;&lt;A class="jive-link-email-small" data-content-finding="Community" href="mailto:root@sabresd_6dq:/"&gt;root@sabresd_6dq:/&lt;/A&gt; # memtool 1ff8000=1&lt;BR /&gt;Writing 32-bit value 0x1 to address 0x01FF8000&lt;BR /&gt;&lt;A class="jive-link-email-small" data-content-finding="Community" href="mailto:root@sabresd_6dq:/"&gt;root@sabresd_6dq:/&lt;/A&gt; #&lt;/P&gt;&lt;P&gt;|&lt;BR /&gt;|&lt;BR /&gt;\/&lt;/P&gt;&lt;P&gt;RC side(console command and kernel message):&lt;/P&gt;&lt;P&gt;&lt;A class="jive-link-email-small" data-content-finding="Community" href="mailto:root@sabresd_6dq:/"&gt;root@sabresd_6dq:/&lt;/A&gt; #&lt;BR /&gt;Test for MSI interrupt - handle_simple_irq triggered by irq: 497&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;A class="jive-link-email-small" data-content-finding="Community" href="mailto:root@sabresd_6dq:/"&gt;root@sabresd_6dq:/&lt;/A&gt; # cat /proc/interrupts | grep MSI&lt;BR /&gt;497:&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 1&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0&amp;nbsp; PCIe-MSI&lt;BR /&gt;&lt;A class="jive-link-email-small" data-content-finding="Community" href="mailto:root@sabresd_6dq:/"&gt;root@sabresd_6dq:/&lt;/A&gt; #&lt;/P&gt;&lt;P&gt;|&lt;BR /&gt;|&lt;BR /&gt;\/&lt;/P&gt;&lt;P&gt;EP side(console command and kernel message):&lt;/P&gt;&lt;P&gt;&lt;A class="jive-link-email-small" data-content-finding="Community" href="mailto:root@sabresd_6dq:/"&gt;root@sabresd_6dq:/&lt;/A&gt; # memtool 1ff8000=1&lt;BR /&gt;Writing 32-bit value 0x1 to address 0x01FF8000&lt;/P&gt;&lt;P&gt;|&lt;BR /&gt;|&lt;BR /&gt;\/&lt;/P&gt;&lt;P&gt;RC side(console command and kernel message):&lt;/P&gt;&lt;P&gt;&lt;A class="jive-link-email-small" data-content-finding="Community" href="mailto:root@sabresd_6dq:/"&gt;root@sabresd_6dq:/&lt;/A&gt; #&lt;BR /&gt;Test for MSI interrupt - handle_simple_irq triggered by irq: 497&lt;/P&gt;&lt;P&gt;&lt;A class="jive-link-email-small" data-content-finding="Community" href="mailto:root@sabresd_6dq:/"&gt;root@sabresd_6dq:/&lt;/A&gt; # cat /proc/interrupts | grep MSI&lt;BR /&gt;497:&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 2&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0&amp;nbsp; PCIe-MSI&lt;BR /&gt;&lt;A class="jive-link-email-small" data-content-finding="Community" href="mailto:root@sabresd_6dq:/"&gt;root@sabresd_6dq:/&lt;/A&gt; #&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Have a great day,&lt;BR /&gt;Jaime&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 08 Sep 2014 15:09:41 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Configuring-i-MX6-as-endpoint-memory-device/m-p/338660#M46269</guid>
      <dc:creator>jamesbone</dc:creator>
      <dc:date>2014-09-08T15:09:41Z</dc:date>
    </item>
    <item>
      <title>Re: Configuring i.MX6 as endpoint memory device</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Configuring-i-MX6-as-endpoint-memory-device/m-p/338661#M46270</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;thanks,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Can you please briefly explain or point me in the right direction to understand the dbi interface, how can I access from my firmware. Apparently I failed to locate that info in reference manual.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Haider&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 08 Sep 2014 18:32:14 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Configuring-i-MX6-as-endpoint-memory-device/m-p/338661#M46270</guid>
      <dc:creator>haider</dc:creator>
      <dc:date>2014-09-08T18:32:14Z</dc:date>
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