<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic i.mx6 SSI in TDM mode in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/i-mx6-SSI-in-TDM-mode/m-p/336859#M45965</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I attached a PCM3168a to the SSI port of the i.mx6q, the codec provides the bit- and wordclocks (imx is slave) and expects data like this:&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="Screenshot from 2015-01-12 18_44_27.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/46039i61F2F18897C25FDB/image-size/large?v=v2&amp;amp;px=999" role="button" title="Screenshot from 2015-01-12 18_44_27.png" alt="Screenshot from 2015-01-12 18_44_27.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;(ti pcm3168a datasheet page 25) bit clock is 11.29MHz&lt;/P&gt;&lt;P&gt;I configured ssi scr to work in networked mode and the ssi stccr is set to 0x16705:&lt;/P&gt;&lt;P&gt;-&amp;gt; word length WL 24 bits&lt;/P&gt;&lt;P&gt;-&amp;gt; 8 words per frame (DC)&lt;/P&gt;&lt;P&gt;I looks like the i.mx6 outputs all 8x24bits back to back, i.e. there's no padding to 32 bits.&lt;/P&gt;&lt;P&gt;I need either 24bits data + 8bits padding or 24bits data + 8 bits padding.&lt;/P&gt;&lt;P&gt;How can I configure the ssi to output such a pattern?&lt;/P&gt;&lt;P&gt;Sending 32 bits with the padding bits set to zero seems to be no option as the WL limit is 24 bits.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Lo2&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Mon, 12 Jan 2015 17:56:02 GMT</pubDate>
    <dc:creator>lo2</dc:creator>
    <dc:date>2015-01-12T17:56:02Z</dc:date>
    <item>
      <title>i.mx6 SSI in TDM mode</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-mx6-SSI-in-TDM-mode/m-p/336859#M45965</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I attached a PCM3168a to the SSI port of the i.mx6q, the codec provides the bit- and wordclocks (imx is slave) and expects data like this:&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="Screenshot from 2015-01-12 18_44_27.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/46039i61F2F18897C25FDB/image-size/large?v=v2&amp;amp;px=999" role="button" title="Screenshot from 2015-01-12 18_44_27.png" alt="Screenshot from 2015-01-12 18_44_27.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;(ti pcm3168a datasheet page 25) bit clock is 11.29MHz&lt;/P&gt;&lt;P&gt;I configured ssi scr to work in networked mode and the ssi stccr is set to 0x16705:&lt;/P&gt;&lt;P&gt;-&amp;gt; word length WL 24 bits&lt;/P&gt;&lt;P&gt;-&amp;gt; 8 words per frame (DC)&lt;/P&gt;&lt;P&gt;I looks like the i.mx6 outputs all 8x24bits back to back, i.e. there's no padding to 32 bits.&lt;/P&gt;&lt;P&gt;I need either 24bits data + 8bits padding or 24bits data + 8 bits padding.&lt;/P&gt;&lt;P&gt;How can I configure the ssi to output such a pattern?&lt;/P&gt;&lt;P&gt;Sending 32 bits with the padding bits set to zero seems to be no option as the WL limit is 24 bits.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Lo2&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 12 Jan 2015 17:56:02 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-mx6-SSI-in-TDM-mode/m-p/336859#M45965</guid>
      <dc:creator>lo2</dc:creator>
      <dc:date>2015-01-12T17:56:02Z</dc:date>
    </item>
    <item>
      <title>Re: i.mx6 SSI in TDM mode</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-mx6-SSI-in-TDM-mode/m-p/336860#M45966</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Lothar&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;you are right WL limit is 24 bits as stated in&lt;/P&gt;&lt;P&gt;&lt;A href="http://cache.freescale.com/files/32bit/doc/ref_manual/IMX6DQRM.pdf?fasp=1&amp;amp;WT_TYPE=Reference%20Manuals&amp;amp;WT_VENDOR=FREESCALE&amp;amp;WT_FILE_FORMAT=pdf&amp;amp;WT_ASSET=Documentation&amp;amp;fileExt=.pdf"&gt;IMX6DQRM&lt;/A&gt; sect.61.1.1 Features :&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Programmable word length (8, 10, 12, 16, 18, 20, 22 or 24 bits)&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;unfortunately, I am afraid it is not possible to extend (or pad in some way) it to 32 bits.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;&lt;P&gt;igor&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;P&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 13 Jan 2015 00:16:50 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-mx6-SSI-in-TDM-mode/m-p/336860#M45966</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2015-01-13T00:16:50Z</dc:date>
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  </channel>
</rss>

