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    <title>topic Receive FIFO for ENET of i.MX6 in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Receive-FIFO-for-ENET-of-i-MX6/m-p/336638#M45890</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Dear All,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Would you teach about receive FIFO registers for ENET of MX6?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;We are referring to the following.&lt;/P&gt;&lt;P&gt;IMX6DQRM.pdf(Rev2)&lt;BR /&gt; - Table 23-130. Receive FIFO thresholds definition(P.1189)&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;We understand that it is necessary to make each register field the following relations.&lt;/P&gt;&lt;P&gt;RSEM &amp;gt; RSFL &amp;gt; RAEM&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;These default values are as follows.&lt;/P&gt;&lt;P&gt; - RSEM = 0x084&lt;BR /&gt; - RSFL = 0x010&lt;BR /&gt; - RAEM = 0x008&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;However, in these values, performance is low.&lt;BR /&gt;If these values are changed as follows, performance will go up.&lt;/P&gt;&lt;P&gt; - RSEM = 0x040&lt;BR /&gt; - RSFL = 0x078&lt;BR /&gt; - RAEM = 0x070&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;We do not understand the reason which performance goes up with these values.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Is the set value to RSFL a value containing RAEM?&lt;BR /&gt;Or, Is the set value to RSFL added value from RAEM?&lt;/P&gt;&lt;P&gt;Would you teach which understanding is right? &lt;/P&gt;&lt;P&gt;&lt;BR /&gt;We would like to set Receive FIFO as 64KByte.&lt;BR /&gt;Can this value be set as Receive FIFO?&lt;BR /&gt;Since the maximum of each field is 0x1FF, 64kByte seems not to be set.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best Regards,&lt;BR /&gt;Yuuki Murasato&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Mon, 20 Oct 2014 11:42:20 GMT</pubDate>
    <dc:creator>yuuki</dc:creator>
    <dc:date>2014-10-20T11:42:20Z</dc:date>
    <item>
      <title>Receive FIFO for ENET of i.MX6</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Receive-FIFO-for-ENET-of-i-MX6/m-p/336638#M45890</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Dear All,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Would you teach about receive FIFO registers for ENET of MX6?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;We are referring to the following.&lt;/P&gt;&lt;P&gt;IMX6DQRM.pdf(Rev2)&lt;BR /&gt; - Table 23-130. Receive FIFO thresholds definition(P.1189)&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;We understand that it is necessary to make each register field the following relations.&lt;/P&gt;&lt;P&gt;RSEM &amp;gt; RSFL &amp;gt; RAEM&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;These default values are as follows.&lt;/P&gt;&lt;P&gt; - RSEM = 0x084&lt;BR /&gt; - RSFL = 0x010&lt;BR /&gt; - RAEM = 0x008&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;However, in these values, performance is low.&lt;BR /&gt;If these values are changed as follows, performance will go up.&lt;/P&gt;&lt;P&gt; - RSEM = 0x040&lt;BR /&gt; - RSFL = 0x078&lt;BR /&gt; - RAEM = 0x070&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;We do not understand the reason which performance goes up with these values.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Is the set value to RSFL a value containing RAEM?&lt;BR /&gt;Or, Is the set value to RSFL added value from RAEM?&lt;/P&gt;&lt;P&gt;Would you teach which understanding is right? &lt;/P&gt;&lt;P&gt;&lt;BR /&gt;We would like to set Receive FIFO as 64KByte.&lt;BR /&gt;Can this value be set as Receive FIFO?&lt;BR /&gt;Since the maximum of each field is 0x1FF, 64kByte seems not to be set.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best Regards,&lt;BR /&gt;Yuuki Murasato&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 20 Oct 2014 11:42:20 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Receive-FIFO-for-ENET-of-i-MX6/m-p/336638#M45890</guid>
      <dc:creator>yuuki</dc:creator>
      <dc:date>2014-10-20T11:42:20Z</dc:date>
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