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    <title>i.MX ProcessorsのトピックRe: Question about gated clock mode</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Question-about-gated-clock-mode/m-p/336011#M45689</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,zhou wei&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I did a test on i.MX6dlsabresdp(which with an ov5642 camera equipped).&lt;/P&gt;&lt;P&gt;After running /unit_test/mxc_v4l2_capture.out with proper parameters,&lt;/P&gt;&lt;P&gt;I read the&lt;EM&gt; &lt;/EM&gt;&lt;STRONG&gt;CSI0 Sensor Configuration Register(IPU_CSI0_SENS_CONF)&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;and value for this register was 0x8900.&lt;/P&gt;&lt;P&gt;According to this value,configurations for CSI0 is as below:&lt;/P&gt;&lt;P&gt;1)data width is 8-bit&lt;/P&gt;&lt;P&gt;2)data format is YUV422 (YUYV...)&lt;/P&gt;&lt;P&gt;3)Timings protocol is Gated mode.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;So, if my understanding of IPU_CSI0_SENS_CONF register is right,&lt;/P&gt;&lt;P&gt;then you can refer to i.MX6dlsabresdp to resolve your problem.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best Regards,&lt;/P&gt;&lt;P&gt;ZongbiaoLiao&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Fri, 06 Feb 2015 10:19:19 GMT</pubDate>
    <dc:creator>宗標廖</dc:creator>
    <dc:date>2015-02-06T10:19:19Z</dc:date>
    <item>
      <title>Question about gated clock mode</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Question-about-gated-clock-mode/m-p/336009#M45687</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; I am using i.mx6 to capture 16bit 4:2:2 YUV signal in gated clock mode. but it does not work like what the datesheet says.&lt;/P&gt;&lt;P style="font-size: 13px; font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif; color: #3d3d3d;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; it is said"&lt;SPAN style="font-family: inherit; line-height: 1.5em; font-style: inherit; text-decoration: underline;"&gt;&lt;STRONG style="font-style: inherit; font-family: inherit;"&gt;Pixel &lt;/STRONG&gt;&lt;/SPAN&gt;&lt;STRONG style="font-family: inherit; line-height: 1.5em; font-style: inherit; text-decoration: underline;"&gt;clock is valid as long as IPU2_CSIx_HSYNC is high. Data is latched at the rising edge of the valid pixel &lt;/STRONG&gt;&lt;STRONG style="font-family: inherit; line-height: 1.5em; font-style: inherit; text-decoration: underline;"&gt;clocks. IPU2_CSIx_HSYNC goes to low at the end of line. Pixel clocks then become invalid and the CSI &lt;/STRONG&gt;&lt;STRONG style="font-family: inherit; line-height: 1.5em; font-style: inherit; text-decoration: underline;"&gt;stops receiving data from the stream&lt;/STRONG&gt;&lt;SPAN style="line-height: 1.5em;"&gt;.&lt;/SPAN&gt;&lt;SPAN style="color: #3d3d3d; font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif; font-size: 13px;"&gt;in &lt;/SPAN&gt;&lt;SPAN style="font-style: inherit; font-family: inherit; color: #3778c7;"&gt;&lt;A href="http://cache.freescale.com/files/32bit/doc/data_sheet/IMX6DQCEC.pdf?fasp=1&amp;amp;WT_TYPE=Data%20Sheets&amp;amp;WT_VENDOR=FREESCALE&amp;amp;WT_FILE_FORMAT=pdf&amp;amp;WT_ASSET=Documentation&amp;amp;fileExt=.pdf"&gt;IMX6DQCEC&lt;/A&gt;&lt;/SPAN&gt;&lt;SPAN style="color: #3d3d3d; font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif; font-size: 13px;"&gt;(section 4.11.10.2.2 Gated Clock Mode). But real situation is that imx6 would capture data when the rising edge of Hsync comes, and imx6 would not stop capturing data even the falling edge comes.&lt;/SPAN&gt;&lt;SPAN style="line-height: 1.5em;"&gt;There may be something wrong.&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="font-size: 13px; font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif; color: #3d3d3d;"&gt;&lt;SPAN style="line-height: 1.5em;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; i haven't found someone &lt;SPAN style="color: #3d3d3d; font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif; font-size: 13px;"&gt;using imx6 to capture data correctly in gated clock mode&lt;/SPAN&gt; in this community but found many peopel facing the same problem. &lt;/SPAN&gt;&lt;/P&gt;&lt;P style="font-size: 13px; font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif; color: #3d3d3d;"&gt;&lt;SPAN style="line-height: 1.5em;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; If&amp;nbsp; there is someone using imx6 to capture data correctly in gated clock mode, could you tell me and give me some advice?&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="font-size: 13px; font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif; color: #3d3d3d;"&gt;&lt;SPAN style="line-height: 1.5em;"&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="font-size: 13px; font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif; color: #3d3d3d;"&gt;&lt;SPAN style="line-height: 1.5em;"&gt;Thanks !&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="font-size: 13px; font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif; color: #3d3d3d;"&gt;&lt;/P&gt;&lt;P style="font-size: 13px; font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif; color: #3d3d3d;"&gt;zhou&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 13 Nov 2014 09:00:20 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Question-about-gated-clock-mode/m-p/336009#M45687</guid>
      <dc:creator>zhouwei</dc:creator>
      <dc:date>2014-11-13T09:00:20Z</dc:date>
    </item>
    <item>
      <title>Re: Question about gated clock mode</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Question-about-gated-clock-mode/m-p/336010#M45688</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi zhou&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;for gated mode one can look below&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.nxp.com/docs/DOC-97981"&gt;How to Support RGB565 Gated Mode Input to i.MX6 CSI&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;you are correct that capture occurs on HSYNC edge as confirmed below&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;A _jive_internal="true" data-containerid="2004" data-containertype="14" data-objectid="360006" data-objecttype="2" href="https://community.nxp.com/message/360006#360006"&gt;Re: IPU v3&amp;nbsp; CSI0, HSYNC and DATA_EN questions in gated clock mode.&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;&lt;P&gt;igor&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 13 Nov 2014 10:34:36 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Question-about-gated-clock-mode/m-p/336010#M45688</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2014-11-13T10:34:36Z</dc:date>
    </item>
    <item>
      <title>Re: Question about gated clock mode</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Question-about-gated-clock-mode/m-p/336011#M45689</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,zhou wei&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I did a test on i.MX6dlsabresdp(which with an ov5642 camera equipped).&lt;/P&gt;&lt;P&gt;After running /unit_test/mxc_v4l2_capture.out with proper parameters,&lt;/P&gt;&lt;P&gt;I read the&lt;EM&gt; &lt;/EM&gt;&lt;STRONG&gt;CSI0 Sensor Configuration Register(IPU_CSI0_SENS_CONF)&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;and value for this register was 0x8900.&lt;/P&gt;&lt;P&gt;According to this value,configurations for CSI0 is as below:&lt;/P&gt;&lt;P&gt;1)data width is 8-bit&lt;/P&gt;&lt;P&gt;2)data format is YUV422 (YUYV...)&lt;/P&gt;&lt;P&gt;3)Timings protocol is Gated mode.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;So, if my understanding of IPU_CSI0_SENS_CONF register is right,&lt;/P&gt;&lt;P&gt;then you can refer to i.MX6dlsabresdp to resolve your problem.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best Regards,&lt;/P&gt;&lt;P&gt;ZongbiaoLiao&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 06 Feb 2015 10:19:19 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Question-about-gated-clock-mode/m-p/336011#M45689</guid>
      <dc:creator>宗標廖</dc:creator>
      <dc:date>2015-02-06T10:19:19Z</dc:date>
    </item>
    <item>
      <title>Re: Question about gated clock mode</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Question-about-gated-clock-mode/m-p/336012#M45690</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello zhou wei.&lt;/P&gt;&lt;P&gt;I have a really same problem !. &lt;/P&gt;&lt;P&gt;If you have a solution or advice, please share for me. &lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 16 Mar 2016 08:43:21 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Question-about-gated-clock-mode/m-p/336012#M45690</guid>
      <dc:creator>hanseunglee</dc:creator>
      <dc:date>2016-03-16T08:43:21Z</dc:date>
    </item>
    <item>
      <title>Re: Question about gated clock mode</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Question-about-gated-clock-mode/m-p/336013#M45691</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;hi all,&lt;/P&gt;&lt;P&gt;I have same problem too!&lt;/P&gt;&lt;P&gt;Do anybody solve it?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 27 Sep 2016 02:19:53 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Question-about-gated-clock-mode/m-p/336013#M45691</guid>
      <dc:creator>lwx</dc:creator>
      <dc:date>2016-09-27T02:19:53Z</dc:date>
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