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    <title>topic device tree with variable number of cpu in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/device-tree-with-variable-number-of-cpu/m-p/334936#M45467</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;If I have an image I want to be able to run in either IMX6Q (4 cores) or IMX6D (2 cores).&lt;/P&gt;&lt;P&gt;Is there a way for the Linux kernel to adjust after number of cores the CPU has or do I need to compile to different images?&lt;/P&gt;&lt;P&gt;In the device tree (for SabreSD there is some configurations for the CPUs, imx6q.dtsi):&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;cpus {&lt;/P&gt;&lt;P&gt;&amp;nbsp; #address-cells = &amp;lt;1&amp;gt;;&lt;/P&gt;&lt;P&gt;&amp;nbsp; #size-cells = &amp;lt;0&amp;gt;;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp; cpu0: cpu@0 {&lt;/P&gt;&lt;P&gt;&amp;nbsp; compatible = "arm,cortex-a9";&lt;/P&gt;&lt;P&gt;&amp;nbsp; device_type = "cpu";&lt;/P&gt;&lt;P&gt;&amp;nbsp; reg = &amp;lt;0&amp;gt;;&lt;/P&gt;&lt;P&gt;&amp;nbsp; next-level-cache = &amp;lt;&amp;amp;L2&amp;gt;;&lt;/P&gt;&lt;P&gt;&amp;nbsp; operating-points = &amp;lt;&lt;/P&gt;&lt;P&gt;&amp;nbsp; /* kHz&amp;nbsp;&amp;nbsp;&amp;nbsp; uV */&lt;/P&gt;&lt;P&gt;&amp;nbsp; 1200000 1275000&lt;/P&gt;&lt;P&gt;&amp;nbsp; 996000&amp;nbsp; 1250000&lt;/P&gt;&lt;P&gt;&amp;nbsp; 852000&amp;nbsp; 1250000&lt;/P&gt;&lt;P&gt;&amp;nbsp; 792000&amp;nbsp; 1150000&lt;/P&gt;&lt;P&gt;&amp;nbsp; 396000&amp;nbsp; 975000&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;gt;;&lt;/P&gt;&lt;P&gt;&amp;nbsp; fsl,soc-operating-points = &amp;lt;&lt;/P&gt;&lt;P&gt;&amp;nbsp; /* ARM kHz&amp;nbsp; SOC-PU uV */&lt;/P&gt;&lt;P&gt;&amp;nbsp; 1200000&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 1275000&lt;/P&gt;&lt;P&gt;&amp;nbsp; 996000&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 1250000&lt;/P&gt;&lt;P&gt;&amp;nbsp; 852000&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 1250000&lt;/P&gt;&lt;P&gt;&amp;nbsp; 792000&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 1175000&lt;/P&gt;&lt;P&gt;&amp;nbsp; 396000&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 1175000&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;gt;;&lt;/P&gt;&lt;P&gt;&amp;nbsp; clock-latency = &amp;lt;61036&amp;gt;; /* two CLK32 periods */&lt;/P&gt;&lt;P&gt;&amp;nbsp; clocks = &amp;lt;&amp;amp;clks 104&amp;gt;, &amp;lt;&amp;amp;clks 6&amp;gt;, &amp;lt;&amp;amp;clks 16&amp;gt;,&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;lt;&amp;amp;clks 17&amp;gt;, &amp;lt;&amp;amp;clks 170&amp;gt;;&lt;/P&gt;&lt;P&gt;&amp;nbsp; clock-names = "arm", "pll2_pfd2_396m", "step",&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; "pll1_sw", "pll1_sys";&lt;/P&gt;&lt;P&gt;&amp;nbsp; arm-supply = &amp;lt;&amp;amp;reg_arm&amp;gt;;&lt;/P&gt;&lt;P&gt;&amp;nbsp; pu-supply = &amp;lt;&amp;amp;reg_pu&amp;gt;;&lt;/P&gt;&lt;P&gt;&amp;nbsp; soc-supply = &amp;lt;&amp;amp;reg_soc&amp;gt;;&lt;/P&gt;&lt;P&gt;&amp;nbsp; };&lt;/P&gt;&lt;P&gt;&amp;nbsp; cpu@1 {&lt;/P&gt;&lt;P&gt;&amp;nbsp; compatible = "arm,cortex-a9";&lt;/P&gt;&lt;P&gt;&amp;nbsp; device_type = "cpu";&lt;/P&gt;&lt;P&gt;&amp;nbsp; reg = &amp;lt;1&amp;gt;;&lt;/P&gt;&lt;P&gt;&amp;nbsp; next-level-cache = &amp;lt;&amp;amp;L2&amp;gt;;&lt;/P&gt;&lt;P&gt;&amp;nbsp; };&lt;/P&gt;&lt;P&gt;&amp;nbsp; cpu@2 {&lt;/P&gt;&lt;P&gt;&amp;nbsp; compatible = "arm,cortex-a9";&lt;/P&gt;&lt;P&gt;&amp;nbsp; device_type = "cpu";&lt;/P&gt;&lt;P&gt;&amp;nbsp; reg = &amp;lt;2&amp;gt;;&lt;/P&gt;&lt;P&gt;&amp;nbsp; next-level-cache = &amp;lt;&amp;amp;L2&amp;gt;;&lt;/P&gt;&lt;P&gt;&amp;nbsp; };&lt;/P&gt;&lt;P&gt;&amp;nbsp; cpu@3 {&lt;/P&gt;&lt;P&gt;&amp;nbsp; compatible = "arm,cortex-a9";&lt;/P&gt;&lt;P&gt;&amp;nbsp; device_type = "cpu";&lt;/P&gt;&lt;P&gt;&amp;nbsp; reg = &amp;lt;3&amp;gt;;&lt;/P&gt;&lt;P&gt;&amp;nbsp; next-level-cache = &amp;lt;&amp;amp;L2&amp;gt;;&lt;/P&gt;&lt;P&gt;&amp;nbsp; };&lt;/P&gt;&lt;P&gt;};&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks,&lt;/P&gt;&lt;P&gt;Niklas&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;TABLE&gt;&lt;TBODY&gt;&lt;TR&gt;&lt;TD&gt;&lt;/TD&gt;&lt;TD&gt;&lt;/TD&gt;&lt;/TR&gt;&lt;/TBODY&gt;&lt;/TABLE&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 24 Feb 2015 23:19:06 GMT</pubDate>
    <dc:creator>niklasmolin</dc:creator>
    <dc:date>2015-02-24T23:19:06Z</dc:date>
    <item>
      <title>device tree with variable number of cpu</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/device-tree-with-variable-number-of-cpu/m-p/334936#M45467</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;If I have an image I want to be able to run in either IMX6Q (4 cores) or IMX6D (2 cores).&lt;/P&gt;&lt;P&gt;Is there a way for the Linux kernel to adjust after number of cores the CPU has or do I need to compile to different images?&lt;/P&gt;&lt;P&gt;In the device tree (for SabreSD there is some configurations for the CPUs, imx6q.dtsi):&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;cpus {&lt;/P&gt;&lt;P&gt;&amp;nbsp; #address-cells = &amp;lt;1&amp;gt;;&lt;/P&gt;&lt;P&gt;&amp;nbsp; #size-cells = &amp;lt;0&amp;gt;;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp; cpu0: cpu@0 {&lt;/P&gt;&lt;P&gt;&amp;nbsp; compatible = "arm,cortex-a9";&lt;/P&gt;&lt;P&gt;&amp;nbsp; device_type = "cpu";&lt;/P&gt;&lt;P&gt;&amp;nbsp; reg = &amp;lt;0&amp;gt;;&lt;/P&gt;&lt;P&gt;&amp;nbsp; next-level-cache = &amp;lt;&amp;amp;L2&amp;gt;;&lt;/P&gt;&lt;P&gt;&amp;nbsp; operating-points = &amp;lt;&lt;/P&gt;&lt;P&gt;&amp;nbsp; /* kHz&amp;nbsp;&amp;nbsp;&amp;nbsp; uV */&lt;/P&gt;&lt;P&gt;&amp;nbsp; 1200000 1275000&lt;/P&gt;&lt;P&gt;&amp;nbsp; 996000&amp;nbsp; 1250000&lt;/P&gt;&lt;P&gt;&amp;nbsp; 852000&amp;nbsp; 1250000&lt;/P&gt;&lt;P&gt;&amp;nbsp; 792000&amp;nbsp; 1150000&lt;/P&gt;&lt;P&gt;&amp;nbsp; 396000&amp;nbsp; 975000&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;gt;;&lt;/P&gt;&lt;P&gt;&amp;nbsp; fsl,soc-operating-points = &amp;lt;&lt;/P&gt;&lt;P&gt;&amp;nbsp; /* ARM kHz&amp;nbsp; SOC-PU uV */&lt;/P&gt;&lt;P&gt;&amp;nbsp; 1200000&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 1275000&lt;/P&gt;&lt;P&gt;&amp;nbsp; 996000&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 1250000&lt;/P&gt;&lt;P&gt;&amp;nbsp; 852000&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 1250000&lt;/P&gt;&lt;P&gt;&amp;nbsp; 792000&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 1175000&lt;/P&gt;&lt;P&gt;&amp;nbsp; 396000&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 1175000&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;gt;;&lt;/P&gt;&lt;P&gt;&amp;nbsp; clock-latency = &amp;lt;61036&amp;gt;; /* two CLK32 periods */&lt;/P&gt;&lt;P&gt;&amp;nbsp; clocks = &amp;lt;&amp;amp;clks 104&amp;gt;, &amp;lt;&amp;amp;clks 6&amp;gt;, &amp;lt;&amp;amp;clks 16&amp;gt;,&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;lt;&amp;amp;clks 17&amp;gt;, &amp;lt;&amp;amp;clks 170&amp;gt;;&lt;/P&gt;&lt;P&gt;&amp;nbsp; clock-names = "arm", "pll2_pfd2_396m", "step",&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; "pll1_sw", "pll1_sys";&lt;/P&gt;&lt;P&gt;&amp;nbsp; arm-supply = &amp;lt;&amp;amp;reg_arm&amp;gt;;&lt;/P&gt;&lt;P&gt;&amp;nbsp; pu-supply = &amp;lt;&amp;amp;reg_pu&amp;gt;;&lt;/P&gt;&lt;P&gt;&amp;nbsp; soc-supply = &amp;lt;&amp;amp;reg_soc&amp;gt;;&lt;/P&gt;&lt;P&gt;&amp;nbsp; };&lt;/P&gt;&lt;P&gt;&amp;nbsp; cpu@1 {&lt;/P&gt;&lt;P&gt;&amp;nbsp; compatible = "arm,cortex-a9";&lt;/P&gt;&lt;P&gt;&amp;nbsp; device_type = "cpu";&lt;/P&gt;&lt;P&gt;&amp;nbsp; reg = &amp;lt;1&amp;gt;;&lt;/P&gt;&lt;P&gt;&amp;nbsp; next-level-cache = &amp;lt;&amp;amp;L2&amp;gt;;&lt;/P&gt;&lt;P&gt;&amp;nbsp; };&lt;/P&gt;&lt;P&gt;&amp;nbsp; cpu@2 {&lt;/P&gt;&lt;P&gt;&amp;nbsp; compatible = "arm,cortex-a9";&lt;/P&gt;&lt;P&gt;&amp;nbsp; device_type = "cpu";&lt;/P&gt;&lt;P&gt;&amp;nbsp; reg = &amp;lt;2&amp;gt;;&lt;/P&gt;&lt;P&gt;&amp;nbsp; next-level-cache = &amp;lt;&amp;amp;L2&amp;gt;;&lt;/P&gt;&lt;P&gt;&amp;nbsp; };&lt;/P&gt;&lt;P&gt;&amp;nbsp; cpu@3 {&lt;/P&gt;&lt;P&gt;&amp;nbsp; compatible = "arm,cortex-a9";&lt;/P&gt;&lt;P&gt;&amp;nbsp; device_type = "cpu";&lt;/P&gt;&lt;P&gt;&amp;nbsp; reg = &amp;lt;3&amp;gt;;&lt;/P&gt;&lt;P&gt;&amp;nbsp; next-level-cache = &amp;lt;&amp;amp;L2&amp;gt;;&lt;/P&gt;&lt;P&gt;&amp;nbsp; };&lt;/P&gt;&lt;P&gt;};&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks,&lt;/P&gt;&lt;P&gt;Niklas&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;TABLE&gt;&lt;TBODY&gt;&lt;TR&gt;&lt;TD&gt;&lt;/TD&gt;&lt;TD&gt;&lt;/TD&gt;&lt;/TR&gt;&lt;/TBODY&gt;&lt;/TABLE&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 24 Feb 2015 23:19:06 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/device-tree-with-variable-number-of-cpu/m-p/334936#M45467</guid>
      <dc:creator>niklasmolin</dc:creator>
      <dc:date>2015-02-24T23:19:06Z</dc:date>
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    <item>
      <title>Re: device tree with variable number of cpu</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/device-tree-with-variable-number-of-cpu/m-p/334937#M45468</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello Niklas,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Are you referring to have the ability to disable/enable cores "on the fly"?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 03 Mar 2015 16:00:49 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/device-tree-with-variable-number-of-cpu/m-p/334937#M45468</guid>
      <dc:creator>SergioSolis</dc:creator>
      <dc:date>2015-03-03T16:00:49Z</dc:date>
    </item>
    <item>
      <title>Re: device tree with variable number of cpu</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/device-tree-with-variable-number-of-cpu/m-p/334938#M45469</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Sergio.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;It's more to not have to recompile the linux image if I want to run it on a both a &lt;SPAN style="color: #3d3d3d; font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif; font-size: 13px;"&gt;IMX6Q and IMX6D.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;I haven't tried to see what happens if I compile it for 4 CPUs and run it on a &lt;SPAN style="color: #3d3d3d; font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif; font-size: 13px;"&gt;IMX6D.&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 03 Mar 2015 16:58:21 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/device-tree-with-variable-number-of-cpu/m-p/334938#M45469</guid>
      <dc:creator>niklasmolin</dc:creator>
      <dc:date>2015-03-03T16:58:21Z</dc:date>
    </item>
    <item>
      <title>Re: device tree with variable number of cpu</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/device-tree-with-variable-number-of-cpu/m-p/334939#M45470</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Niklas,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;You'd be better off adding 'maxcpus=' to the kernel command line in u-boot.&amp;nbsp; No recompiling necessary.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Cheers,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Glen&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 03 Mar 2015 17:42:52 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/device-tree-with-variable-number-of-cpu/m-p/334939#M45470</guid>
      <dc:creator>gfine</dc:creator>
      <dc:date>2015-03-03T17:42:52Z</dc:date>
    </item>
    <item>
      <title>Re: device tree with variable number of cpu</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/device-tree-with-variable-number-of-cpu/m-p/334940#M45471</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Glen.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks for the information.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I should have a check in the u-boot which type of CPU it is and then just set the &lt;SPAN style="color: #3d3d3d; font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif; font-size: 13px;"&gt;maxcpus= when I start kernel.&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 03 Mar 2015 18:22:48 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/device-tree-with-variable-number-of-cpu/m-p/334940#M45471</guid>
      <dc:creator>niklasmolin</dc:creator>
      <dc:date>2015-03-03T18:22:48Z</dc:date>
    </item>
    <item>
      <title>Re: device tree with variable number of cpu</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/device-tree-with-variable-number-of-cpu/m-p/334941#M45472</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Niklas,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I think the code isalready there as u-boot.imx is usable across most of the i.MX6 series (except 6Solo).&amp;nbsp; So there may not even be a need to use maxcpus.&amp;nbsp; Only use maxcpus if you need a 6Q to act like a 6D. &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Your initial question was if there was a way to do this without recompiling the kernel or the device tree, and that is what the 'maxcpus' kernel command is usually used for. Otherwise u-boot.imx should suffice.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Cheers,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Glen&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 03 Mar 2015 19:28:05 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/device-tree-with-variable-number-of-cpu/m-p/334941#M45472</guid>
      <dc:creator>gfine</dc:creator>
      <dc:date>2015-03-03T19:28:05Z</dc:date>
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