topic Re: Maximum size of ldb in i.MX6DQ. in i.MX Processors

Maximum size of ldb in i.MX6DQ.

keitanagashima — Tue, 05 Aug 2014 05:26:27 GMT

Dear Sir or Madam,

Hello.

Could you tell me the maximum output size of ldb with single channel mode in i.MX6DQ ?

Refer to MCIMX6DQRM(Rev.2).

Is this right? I consider that dual input data interface case is higher performance than single input data interface case.

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Overall: LDB supports rates needed by WUXGA 16:10 aspect ratio (1920 x 1200 @60 frames per second, data rate supported up to 170 MHz)

• For single input data interface case: Up to 170 MHz pixel clock (WUXGA1920x1200)

• For dual input data interface case: Up to 85 MHz per interface. (WXGA 1366x768 @60 frames per second, 35% blanking).

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Best Regards,

Keita

Re: Maximum size of ldb in i.MX6DQ.

igorpadykov — Tue, 05 Aug 2014 06:20:42 GMT

Hi Keita

Seems WUXGA (1920x1200) is possible only for split channel mode,

in all other cases max. is WXGA (1366x768) per output channel.

Limitation is from max. serializer clock 595MHz, which limits

channel frequency to 1/7=85MHz interface pixel clock per channel.

Best regards

chip

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Re: Maximum size of ldb in i.MX6DQ.

keitanagashima — Tue, 05 Aug 2014 07:50:56 GMT

Dear chipexpert,

Hello.

Thank you for your prompt reply.

Sorry. I am confused.

I'd like to know the maximum output size of ldb with single channel mode in i.MX6DQ.

I found below description in freescale's internal doc.

- Single Channel (up to WXGA): Up to 85 MHz, 3 or 4 data pairs

- Dual Channel (up to UXGA): Up to 170 MHz, 6 or 8 data pairs

Let me clarify my understanding. If you find my mistake, please tell me.

My understanding is below;

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Single Channel : up to WXGA

IPU0(DI0) --> ldb0 --> LVDS Display

Split Cannel : up to WXGA

IPU0 (DI0-odd) --> ldb0 --> LVDS0

IPU0 (DI0-even) --> ldb1 --> LVDS1

Dual Cannel : up to UXGA <----- Why is it size up to UXGA? I couldn't understood it.

IPU0 (DI0) --> ldb0 --> LVDS0

IPU0 (DI0) --> ldb1 --> LVDS1

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Best Regards,

Keita

Re: Maximum size of ldb in i.MX6DQ.

mahi — Tue, 05 Aug 2014 08:37:27 GMT

Hello,

in my opinion MCIMX6DQRM is quite confusing. Here is what I understood do far:

It says up to 170MHz for single input.

It also says that the serializers support up to 595MHz...

595MHz divided by 7 slots is 85MHz. So each LDVS output supports a maximum of 85MHz PixelClock.

In Dual Channels mode, one input (DI0 or DI1) with up to 85MHz is spread onto two displays having the same content. So Dual Channel supports two "cloned" displays with e.g. 1366x768@60 each.

In Split Channels mode,one input (DI0 or DI1) with up to 170MHz is separated into even and odd pixels for one display with two LVDS-channels (up to 1920x1200@60).

Separate Channels mode has 85MHz inputs and outputs (each supporting WXGA).

@chipexpert: Please correct me if I'm wrong.

Re: Maximum size of ldb in i.MX6DQ.

igorpadykov — Tue, 05 Aug 2014 11:34:02 GMT

Hi Martin

I think you are right.

Best regards

chip