<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Missing DRAM lines in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Missing-DRAM-lines/m-p/334229#M45346</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello. In my application I am trying to couple i.MX6 with standard 240-pin DDR3 UDIMM. I've noticed that DDR3 UDIMM specifications imply that you have DQM8 and SDQS8 (and inverted /SDQS8), but there are no such pins on i.MX6. As i understand this can lead to misclocking some chips on DIMM memory device. &lt;/P&gt;&lt;P&gt;Is there any way to fix such trouble? Like duplicating other signal or faking it? Or any other way?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Sun, 11 Jan 2015 15:12:33 GMT</pubDate>
    <dc:creator>olegpereverzev</dc:creator>
    <dc:date>2015-01-11T15:12:33Z</dc:date>
    <item>
      <title>Missing DRAM lines</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Missing-DRAM-lines/m-p/334229#M45346</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello. In my application I am trying to couple i.MX6 with standard 240-pin DDR3 UDIMM. I've noticed that DDR3 UDIMM specifications imply that you have DQM8 and SDQS8 (and inverted /SDQS8), but there are no such pins on i.MX6. As i understand this can lead to misclocking some chips on DIMM memory device. &lt;/P&gt;&lt;P&gt;Is there any way to fix such trouble? Like duplicating other signal or faking it? Or any other way?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sun, 11 Jan 2015 15:12:33 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Missing-DRAM-lines/m-p/334229#M45346</guid>
      <dc:creator>olegpereverzev</dc:creator>
      <dc:date>2015-01-11T15:12:33Z</dc:date>
    </item>
    <item>
      <title>Re: Missing DRAM lines</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Missing-DRAM-lines/m-p/334230#M45347</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;He Oleg&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;seems it can not be used with i.MX6, in general you can&lt;/P&gt;&lt;P&gt;look at datasheet and try to understand purpose of DQM8 and SDQS8.&lt;/P&gt;&lt;P&gt;I doubt if it can be "duplicated" or "fixed" by some way.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;&lt;P&gt;igor&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 12 Jan 2015 00:36:29 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Missing-DRAM-lines/m-p/334230#M45347</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2015-01-12T00:36:29Z</dc:date>
    </item>
    <item>
      <title>Re: Missing DRAM lines</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Missing-DRAM-lines/m-p/334231#M45348</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&amp;nbsp; The 9-th [DQM8 and SDQS8 (and inverted /SDQS8)] is used for checking.&lt;BR /&gt; The i.MX6 memory controller does not support it.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;~Yuri.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 12 Jan 2015 03:22:45 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Missing-DRAM-lines/m-p/334231#M45348</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2015-01-12T03:22:45Z</dc:date>
    </item>
    <item>
      <title>Re: Missing DRAM lines</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Missing-DRAM-lines/m-p/334232#M45349</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Thanks. So if I will use non-ECC memory I can ignore those pins?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 12 Jan 2015 07:47:02 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Missing-DRAM-lines/m-p/334232#M45349</guid>
      <dc:creator>olegpereverzev</dc:creator>
      <dc:date>2015-01-12T07:47:02Z</dc:date>
    </item>
    <item>
      <title>Re: Missing DRAM lines</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Missing-DRAM-lines/m-p/334233#M45350</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Probably yes.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 12 Jan 2015 07:54:27 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Missing-DRAM-lines/m-p/334233#M45350</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2015-01-12T07:54:27Z</dc:date>
    </item>
    <item>
      <title>Re: Missing DRAM lines</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Missing-DRAM-lines/m-p/334234#M45351</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Thanks, I'll give it a try.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 12 Jan 2015 08:08:19 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Missing-DRAM-lines/m-p/334234#M45351</guid>
      <dc:creator>olegpereverzev</dc:creator>
      <dc:date>2015-01-12T08:08:19Z</dc:date>
    </item>
  </channel>
</rss>

