topic Re: controlling GIC pin CFGSDISABLE in i.MX Processors

controlling GIC pin CFGSDISABLE

st68 — Tue, 02 Sep 2014 16:23:50 GMT

I'm using an IMX6Q.

I’ve been trying to determine how the CFGSDISABLE line of the GIC is set/cleared.

Can anyone help me with this?

Re: controlling GIC pin CFGSDISABLE

jamesbone — Thu, 04 Sep 2014 13:15:04 GMT

A GIC that implements the Security Extensions can also implement configuration lockdown. This provides a control signal that the system can assert to prevent write access to the register fields controlling a configured range of SPIs, when those SPIs are configured as Secure interrupts, and to some configuration registers. When the control signal is asserted, the Secure SPIs and configuration registers are described as being locked down.

Lockdown is controlled by an active HIGH disable signal, CFGSDISABLE. That is, the system asserts

CFGSDISABLE HIGH to disable write access to the register fields and registers.

Have a great day,
Jaime

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Re: controlling GIC pin CFGSDISABLE

st68 — Thu, 04 Sep 2014 19:50:01 GMT

Jaime,

I've found CFGSDISABLE is defined in ARM's GIC manual (has the information you posted above), is mentioned once in the i.MX6 processor reference manual, and is not mentioned in the Security manual.

What I'm specifically trying to determine is how the system (the IMX6Q) asserts CFGSDISABLE HIGH. Is it an external pin on the chip? Is it set in the SNVS somehow? Is it connected to an internal GPIO pin?

Thanks in advance for any pointers,

Stan

Re: controlling GIC pin CFGSDISABLE

jamesbone — Thu, 11 Sep 2014 12:49:56 GMT

Hello,

Hello Stan,

The information that you are looking for it is on the i.MX6 Security Reference Manual but this information it is consider sensitive so we are not allow to share it in public, you can download the manual from this link:

i.MX6Q|i.MX 6Quad Processors|Quad Core|Freescale

Naturally, we cannot discuss this with you in public anyway, this requires to be handled as a Service Request (SR). Be aware that to give you remote support through a SR.

Have a great day,
Jaime

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