topic Re: IMX6S supply sequence in i.MX Processors

IMX6S supply sequence

王剑翰 — Mon, 08 Dec 2014 10:49:22 GMT

I found the power-up sequence restrictions in 4.2.1 Power-Up Sequence of IMX6SDLIEC.pdf.

My customer not use external SRC_POR_B signal(left unconnected) and also not use PMIC design. Other design is refer to SPF-27516_C3.pdf(Sabre_sdb Schematics).

Their design's power-up sequence is also not same with SPF-27516_C3.pdf(Sabre_sdb Schematics).

1)Customer's 1.425V supply(VDD_SOC/VDD_ARM_IN) power up after the DDR3 supply(the sequence is not the same with the Sabre_sdb supply sequence).

2)In Sabre_sdb supply sequence, DDR_VREF power up in the same sequence with DDR_1.5V. But in customer's design, VREFDDR0.75V power up before DDR3 1.5V supply(more than 14.5ms).

I don't know whether the sequence is OK as I can not find any restrictions information for the case.

Thank you for your help and look forward to your kindly answer.

Re: IMX6S supply sequence

Yuri — Mon, 08 Dec 2014 11:25:54 GMT

I think Your power up sequence can violate the next restriction :

All i.MX6 I/O pins should not be externally driven while the I/O power supply
for the pin (NVCC_xxx) is OFF. This can cause internal latch-up and malfunctions
due to reverse current flows.

The recommended power up sequence (agree - it is not clearly described) is as following :

1) VDD_SNVS_IN (+optional VDD_HIGH_IN)

2) VDD_ARMx_IN / VDD_SOC_IN

3) all other supplies.

Have a great day,

Yuri

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Re: IMX6S supply sequence

王剑翰 — Tue, 09 Dec 2014 06:30:39 GMT

Hi Yuri,

Thank you for your kindly answer.

Could you help to give a reason about the VDD_ARMx_IN / VDD_SOC_IN should be power-up before all other supplies except VDD_SNVS_IN?

Re: IMX6S supply sequence

Yuri — Thu, 11 Dec 2014 08:50:17 GMT

Providing VDD_ARMx_IN / VDD_SOC_IN power-up before all other supplies allows to avoid unpredictable
(GPIO) pin states during power up.

~Yuri.