topic Re: iMX6 Clock Root Generator figures wrong or not? in i.MX Processors https://community.nxp.com/t5/i-MX-Processors/iMX6-Clock-Root-Generator-figures-wrong-or-not/m-p/331308#M44746 <HTML><HEAD></HEAD><BODY><P>So, just to confirm; the figures under <SPAN style="color: #3d3d3d; font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif;">section 18.5.1.5.4 Clock Root Generator</SPAN> should show (cg) for the PCIE, VD_AXI, CAN_CLK and UART signals? There is nothing "different" with the clock gating than any of the other signals, correct?</P></BODY></HTML> Sun, 03 Aug 2014 21:17:26 GMT MichaelV 2014-08-03T21:17:26Z iMX6 Clock Root Generator figures wrong or not? https://community.nxp.com/t5/i-MX-Processors/iMX6-Clock-Root-Generator-figures-wrong-or-not/m-p/331306#M44744 <HTML><HEAD></HEAD><BODY><P>Hi,</P><P></P><P>iMX6SDL/DQ RM section 18.5.1.5.4 Clock Root Generator.</P><P></P><P>The figures in that chapter show the locations of the Clock Gates. T<SPAN style="font-size: 10pt; line-height: 1.5em;">he following signals show no gate (cg) in the figure, but they do have a gate according to the CCGRn registers:</SPAN></P><P></P><UL><LI>PCIE</LI><LI>VDO_AXI</LI><LI>CAN_CLK</LI><LI>UART</LI></UL><P></P><P></P><P>Is this a documentation error, or does it mean these signals are really different than the others (maybe gated at a later stage)?</P></BODY></HTML> Sun, 03 Aug 2014 09:57:38 GMT https://community.nxp.com/t5/i-MX-Processors/iMX6-Clock-Root-Generator-figures-wrong-or-not/m-p/331306#M44744 MichaelV 2014-08-03T09:57:38Z Re: iMX6 Clock Root Generator figures wrong or not? https://community.nxp.com/t5/i-MX-Processors/iMX6-Clock-Root-Generator-figures-wrong-or-not/m-p/331307#M44745 <HTML><HEAD></HEAD><BODY><P>Hi Michel</P><P></P><P>correct description is given in <SPAN style="font-size: 10pt;">CCGRn registers.</SPAN></P><P><SPAN style="font-size: 10pt;"><BR /></SPAN></P><P>Best regards</P><P>chip</P><P>-----------------------------------------------------------------------------------------------------------------------</P><P>Note: If this post answers your question, please click the Correct Answer button. Thank you!</P><P>-----------------------------------------------------------------------------------------------------------------------</P></BODY></HTML> Sun, 03 Aug 2014 14:06:27 GMT https://community.nxp.com/t5/i-MX-Processors/iMX6-Clock-Root-Generator-figures-wrong-or-not/m-p/331307#M44745 igorpadykov 2014-08-03T14:06:27Z Re: iMX6 Clock Root Generator figures wrong or not? https://community.nxp.com/t5/i-MX-Processors/iMX6-Clock-Root-Generator-figures-wrong-or-not/m-p/331308#M44746 <HTML><HEAD></HEAD><BODY><P>So, just to confirm; the figures under <SPAN style="color: #3d3d3d; font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif;">section 18.5.1.5.4 Clock Root Generator</SPAN> should show (cg) for the PCIE, VD_AXI, CAN_CLK and UART signals? There is nothing "different" with the clock gating than any of the other signals, correct?</P></BODY></HTML> Sun, 03 Aug 2014 21:17:26 GMT https://community.nxp.com/t5/i-MX-Processors/iMX6-Clock-Root-Generator-figures-wrong-or-not/m-p/331308#M44746 MichaelV 2014-08-03T21:17:26Z Re: iMX6 Clock Root Generator figures wrong or not? https://community.nxp.com/t5/i-MX-Processors/iMX6-Clock-Root-Generator-figures-wrong-or-not/m-p/331309#M44747 <HTML><HEAD></HEAD><BODY><P>Yes, correct</P><P></P><P>Best regards</P><P>chip</P></BODY></HTML> Sun, 03 Aug 2014 23:15:15 GMT https://community.nxp.com/t5/i-MX-Processors/iMX6-Clock-Root-Generator-figures-wrong-or-not/m-p/331309#M44747 igorpadykov 2014-08-03T23:15:15Z