EIM correct wait cycles between CSs

norishinozaki — Mon, 10 Nov 2014 11:04:01 GMT

Hello Champs,

We would like to determine the correct wait cycles between 2 CSs in EIM.

We figured out following cycles from the i.MX21 reference manual.

However we are not sure if we have correct understanding.

Could you check if following values are correct not?

I. Regarding CNC

1. In CS[4], we set WSC=2, CNC=3, EDC=0, CSA=CSN=0

1-1. After a Read access to CS[4],

a. A Read access to the same CS[4] delayed 3 HCLK cycles?

b. A Read access to CS[2] delayed 3 HCLK cycles?

c. A Write access to the same CS[4] 3 HCLK cycles?

d. A Write access to CS[2] delayed 3 HCLK cycles?

1-2. After a Write access to CS[4],

a. A Read access to the same CS[4] delayed 3 HCLK cycles?

b. A Read access to CS[2] delayed 3 HCLK cycles?

c. A Write access to the same CS[4] 3 HCLK cycles?

d. A Write access to CS[2] delayed 3 HCLK cycles?

2. In CS[4], we set WSC=4, CNC=3, EDC=0, CSA=1, CSN=0

2-1. After a Read access to CS[4],

(The same questions as 1-1)

a. A Read access to the same CS[4] delayed 3 HCLK cycles

b. A Read access to CS[2] delayed 3 HCLK cycles

c. A Write access to the same CS[4] 3 HCLK cycles

d. A Write access to CS[2] delayed 3 HCLK cycles

2-2. After a Write access to CS[4],

a. A Read access to the same CS[4] delayed 0 HCLK cycles?

b. A Read access to CS[2] delayed 0 HCLK cycles?

c. A Write access to the same CS[4] 0 HCLK cycles?

d. A Write access to CS[2] delayed 0 HCLK cycles?

3. In CS[4], we set WSC=4, CNC=3, EDC=0, CSA=0, CSN=1

3-1. After a Read access to CS[4],

(The same questions as 1-1)

a. A Read access to the same CS[4] delayed 3 HCLK cycles?

b. A Read access to CS[2] delayed 3 HCLK cycles?

c. A Write access to the same CS[4] 3 HCLK cycles?

d. A Write access to CS[2] delayed 3 HCLK cycles?

3-2. After a Write access to CS[4],

(The same questions as 2-2)

a. A Read access to the same CS[4] delayed 0 HCLK cycles?

b. A Read access to CS[2] delayed 0 HCLK cycles?

c. A Write access to the same CS[4] 0 HCLK cycles?

d. A Write access to CS[2] delayed 0 HCLK cycles?

II. Regarding EDC

4. In CS[4], we set WSC=2, CNC=0, EDC=2, CSA=CSN=0

4-1. After a Read access to CS[4],

a. A Read access to the same CS[4] delayed 0 HCLK cycle?

b. A Read access to CS[2] delayed 2 HCLK cycles?

c. A Write access to the same CS[4] 2 HCLK cycles?

d. A Write access to CS[2] delayed 2 HCLK cycles?

4-2. After a Write access to CS[4],

(The same questions as 2-2)

a. A Read access to the same CS[4] delayed 0 HCLK cycles?

b. A Read access to CS[2] delayed 0 HCLK cycles?

c. A Write access to the same CS[4] 0 HCLK cycles?

d. A Write access to CS[2] delayed 0 HCLK cycles?

III. Combination of CNC and EDC

5. In CS[4], we set WSC=2, CNC=3, EDC=2, CSA=CSN=0

5-1. After a Read access to CS[4],

a. A Read access to the same CS[4] delayed 3 HCLK cycles?

b. A Read access to CS[2] delayed 3+2 HCLK cycles?

c. A Write access to the same CS[4] 3+2 HCLK cycles?

d. A Write access to CS[2] delayed 3+2 HCLK cycles?

5-2. After a Write access to CS[4],

(The same questions as 1-1?)

a. A Read access to the same CS[4] delayed 3 HCLK cycles?

b. A Read access to CS[2] delayed 3 HCLK cycles?

c. A Write access to the same CS[4] 3 HCLK cycles?

d. A Write access to CS[2] delayed 3 HCLK cycles?

6. In CS[4], we set WSC=4, CNC=3, EDC=2, CSA=1, CSN=0

6-1. After a Read access to CS[4],

(The same questions as 5-1?)

a. A Read access to the same CS[4] delayed 3 HCLK cycles?

b. A Read access to CS[2] delayed 3+2 HCLK cycles?

c. A Write access to the same CS[4] 3+2 HCLK cycles?

d. A Write access to CS[2] delayed 3+2 HCLK cycles?

6-2. After a Write access to CS[4],

(The same questions as 2-2)

a. A Read access to the same CS[4] delayed 0 HCLK cycles?

b. A Read access to CS[2] delayed 0 HCLK cycles?

c. A Write access to the same CS[4] 0 HCLK cycles?

d. A Write access to CS[2] delayed 0 HCLK cycles?

7. In CS[4], we set WSC=4, CNC=3, EDC=2, CSA=0, CSN=1

7-1. After a Read access to CS[4],

(The same questions as 5-1?)

a. A Read access to the same CS[4] delayed 3 HCLK cycles?

b. A Read access to CS[2] delayed 3+2 HCLK cycles?

c. A Write access to the same CS[4] 3+2 HCLK cycles?

d. A Write access to CS[2] delayed 3+2 HCLK cycles?

7-2. After a Write access to CS[4],

(The same questions as 2-2)

a. A Read access to the same CS[4] delayed 0 HCLK cycles?

b. A Read access to CS[2] delayed 0 HCLK cycles?

c. A Write access to the same CS[4] 0 HCLK cycles?

d. A Write access to CS[2] delayed 0 HCLK cycles?

Best regards,

Nori Shinozaki

i.MX ProcessorsのトピックEIM correct wait cycles between CSs

EIM correct wait cycles between CSs