topic Problem halting iMX6 Chips (ARM Cortex-A9) at reset in i.MX Processors

Problem halting iMX6 Chips (ARM Cortex-A9) at reset

nathanpalmer — Wed, 30 Jul 2014 20:04:52 GMT

Has anyone figured out how to halt the iMX6 (Cortex-A9) CPU just after or at reset? My reset-init is taking too long to halt and I am ending up with a non-predictable system debug environment. It loads the CPU boot ROM and is well into initializing my boot loader (U-Boot) before the halt takes affect.

In order to use OpenOCD I have to erase U-Boot from FLASH, and even then the ROM boot code is executed.

I am hoping that some one here has a clue on making a more reliable iMX6 (actually an iMX6sl) debug environment.

Thanks!

Re: Problem halting iMX6 Chips (ARM Cortex-A9) at reset

leoschwab — Wed, 30 Jul 2014 20:28:48 GMT

Based on by disjointed readings on the subject, I think the semi-official method on the i.MX6 series is to force the device into serial bootloader mode (BOOT_MODE0 == 1, BOOT_MODE1 == 0), leaving the USB port unconnected. When halt finally takes effect, the PC will be in the on-chip ROM waiting for a USB connection. Change the PC to where you want and resume the CPU from there ('resume <address>'). At the very least, U-Boot won't have been loaded or run.

Please note that I have not had any actual success doing this myself, as I outlined here.

Re: Problem halting iMX6 Chips (ARM Cortex-A9) at reset

nathanpalmer — Thu, 31 Jul 2014 15:51:52 GMT

That sucks for boards that don't have jumpers for that (production boards). Is there a plan or at least a technical approach to support reset halts in OpenOCD for the MX6? Sorry to ask OpenOCD questions here, I just suspect that the audience would have run across this issue before and may be tracking it.

Re: Problem halting iMX6 Chips (ARM Cortex-A9) at reset

Yuri — Fri, 01 Aug 2014 01:32:35 GMT

The only i.MX35 of i.MX series has special so called startup mode :

"Upon reset the PC register will remain at address 0x00000000.
This means no ROM code has run so far and the state of all internal
SOC registers are untouched."

Perhaps, the fact, that it is impossible to stop the ARM core just
after reset relates to HAB technology - to avoid ROM code hacking.