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    <title>i.MX ProcessorsのトピックRe: IMX6Q L2 Cache TAG and RAM latency settings?</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/IMX6Q-L2-Cache-TAG-and-RAM-latency-settings/m-p/325704#M43727</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;We’re investigating what the final figure should be. I’ll let you know as soon as we have an update.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Mon, 30 Jun 2014 19:39:08 GMT</pubDate>
    <dc:creator>gusarambula</dc:creator>
    <dc:date>2014-06-30T19:39:08Z</dc:date>
    <item>
      <title>IMX6Q L2 Cache TAG and RAM latency settings?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX6Q-L2-Cache-TAG-and-RAM-latency-settings/m-p/325703#M43726</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;In the IMX6 Quad technical reference manual I see that Table 12-5 “PL310 L2 Cache Configuration” (see pg 569 of the i.MX 6Dual/6Quad Applications Processor Reference Manual, Rev. 1, 04/2013), specifies “RAM&amp;nbsp;&amp;nbsp; Latencies” as 4 and has a footnote that 4 is a preliminary value, final value is TBD. &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;What is the final value that should be used when setting the PL310 TAG RAM and DATA RAM latency control registers?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 27 Jun 2014 19:07:15 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX6Q-L2-Cache-TAG-and-RAM-latency-settings/m-p/325703#M43726</guid>
      <dc:creator>jonwatson</dc:creator>
      <dc:date>2014-06-27T19:07:15Z</dc:date>
    </item>
    <item>
      <title>Re: IMX6Q L2 Cache TAG and RAM latency settings?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX6Q-L2-Cache-TAG-and-RAM-latency-settings/m-p/325704#M43727</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;We’re investigating what the final figure should be. I’ll let you know as soon as we have an update.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 30 Jun 2014 19:39:08 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX6Q-L2-Cache-TAG-and-RAM-latency-settings/m-p/325704#M43727</guid>
      <dc:creator>gusarambula</dc:creator>
      <dc:date>2014-06-30T19:39:08Z</dc:date>
    </item>
    <item>
      <title>Re: IMX6Q L2 Cache TAG and RAM latency settings?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX6Q-L2-Cache-TAG-and-RAM-latency-settings/m-p/325705#M43728</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I apologize. I couldn’t locate this specific information but may I ask why do you need this parameter? Maybe we can help with some other information.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 25 Jul 2014 15:50:16 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX6Q-L2-Cache-TAG-and-RAM-latency-settings/m-p/325705#M43728</guid>
      <dc:creator>gusarambula</dc:creator>
      <dc:date>2014-07-25T15:50:16Z</dc:date>
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