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    <title>topic iMX6 PCIe capability in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/iMX6-PCIe-capability/m-p/322055#M43032</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi guys.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;I'm not familiar with i.MX6 PCIe and I want to know several things as following.&lt;/P&gt;&lt;P&gt;* How many virtual channels(VC) can be handle by PCIe?&lt;/P&gt;&lt;P&gt;* Is there any possibility to occur cache incoherence when PCIe access to DRAM?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;If someone knows, please let me know. &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Fri, 18 Jul 2014 12:54:07 GMT</pubDate>
    <dc:creator>torus1000</dc:creator>
    <dc:date>2014-07-18T12:54:07Z</dc:date>
    <item>
      <title>iMX6 PCIe capability</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX6-PCIe-capability/m-p/322055#M43032</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi guys.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;I'm not familiar with i.MX6 PCIe and I want to know several things as following.&lt;/P&gt;&lt;P&gt;* How many virtual channels(VC) can be handle by PCIe?&lt;/P&gt;&lt;P&gt;* Is there any possibility to occur cache incoherence when PCIe access to DRAM?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;If someone knows, please let me know. &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 18 Jul 2014 12:54:07 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX6-PCIe-capability/m-p/322055#M43032</guid>
      <dc:creator>torus1000</dc:creator>
      <dc:date>2014-07-18T12:54:07Z</dc:date>
    </item>
    <item>
      <title>Re: iMX6 PCIe capability</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX6-PCIe-capability/m-p/322056#M43033</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi torus1000&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;there are 8 VC [in particular sect.48.9.22 VCn.. &lt;A href="http://cache.freescale.com/files/32bit/doc/ref_manual/IMX6DQRM.pdf?fasp=1&amp;amp;WT_TYPE=Reference%20Manuals&amp;amp;WT_VENDOR=FREESCALE&amp;amp;WT_FILE_FORMAT=pdf&amp;amp;WT_ASSET=Documentation"&gt;IMX6DQRM&lt;/A&gt; points on this].&lt;/P&gt;&lt;P&gt;Regarding "possibility to occur cache incoherence" I think&lt;/P&gt;&lt;P&gt;no, because PCIe is serviced by arm core, it has not own DMA engine.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;&lt;P&gt;chip&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;P&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 18 Jul 2014 16:18:03 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX6-PCIe-capability/m-p/322056#M43033</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2014-07-18T16:18:03Z</dc:date>
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