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    <title>topic I.MX6Q MIPI-CSI2 voltage level in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/I-MX6Q-MIPI-CSI2-voltage-level/m-p/321707#M42958</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;SPAN style="color: #1f497d;"&gt;Hi there,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #1f497d;"&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #1f497d;"&gt;We are using I.MX6Q in one of our solutions in which we are utilizing MIPI-CSI2 for acquiring HDMI &lt;STRONG&gt;&lt;EM&gt;input.&lt;/EM&gt;&lt;/STRONG&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #1f497d;"&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #1f497d;"&gt;In the datasheet of Toshiba HDMI to MIPI-CSI2 bridge IC, TC358747, it is mentioned that VDD_MIPI is of 1.2V level, refer to the below image.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #1f497d;"&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #1f497d;"&gt;&lt;span class="lia-inline-image-display-wrapper"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/42760i4A7876852B25A1E2/image-size/large?v=v2&amp;amp;px=999" title="bridge_level.png" alt="bridge_level.png" /&gt;&lt;/span&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #1f497d;"&gt;Whereas it is mentioned in Page 22 of I.MX6Q datasheet that NVCC_CSI is of 1.8V level, refer to the below image.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #1f497d;"&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #1f497d;"&gt;&lt;span class="lia-inline-image-display-wrapper"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/42809iAF22A2A3DAB0EFFA/image-size/large?v=v2&amp;amp;px=999" title="processor_level.png" alt="processor_level.png" /&gt;&lt;/span&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #1f497d;"&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #1f497d;"&gt;We understand that both these rails are only the core voltage levels and does it not have any significance on the differential signaling levels and therefore this is not a conflict. &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #1f497d;"&gt;Kindly let us know whether our understanding is correct and help us make sure that our design is correct.&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 19 Jun 2014 12:57:16 GMT</pubDate>
    <dc:creator>vigneshvasudeva</dc:creator>
    <dc:date>2014-06-19T12:57:16Z</dc:date>
    <item>
      <title>I.MX6Q MIPI-CSI2 voltage level</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/I-MX6Q-MIPI-CSI2-voltage-level/m-p/321707#M42958</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;SPAN style="color: #1f497d;"&gt;Hi there,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #1f497d;"&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #1f497d;"&gt;We are using I.MX6Q in one of our solutions in which we are utilizing MIPI-CSI2 for acquiring HDMI &lt;STRONG&gt;&lt;EM&gt;input.&lt;/EM&gt;&lt;/STRONG&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #1f497d;"&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #1f497d;"&gt;In the datasheet of Toshiba HDMI to MIPI-CSI2 bridge IC, TC358747, it is mentioned that VDD_MIPI is of 1.2V level, refer to the below image.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #1f497d;"&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #1f497d;"&gt;&lt;span class="lia-inline-image-display-wrapper"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/42760i4A7876852B25A1E2/image-size/large?v=v2&amp;amp;px=999" title="bridge_level.png" alt="bridge_level.png" /&gt;&lt;/span&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #1f497d;"&gt;Whereas it is mentioned in Page 22 of I.MX6Q datasheet that NVCC_CSI is of 1.8V level, refer to the below image.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #1f497d;"&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #1f497d;"&gt;&lt;span class="lia-inline-image-display-wrapper"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/42809iAF22A2A3DAB0EFFA/image-size/large?v=v2&amp;amp;px=999" title="processor_level.png" alt="processor_level.png" /&gt;&lt;/span&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #1f497d;"&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #1f497d;"&gt;We understand that both these rails are only the core voltage levels and does it not have any significance on the differential signaling levels and therefore this is not a conflict. &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #1f497d;"&gt;Kindly let us know whether our understanding is correct and help us make sure that our design is correct.&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 19 Jun 2014 12:57:16 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/I-MX6Q-MIPI-CSI2-voltage-level/m-p/321707#M42958</guid>
      <dc:creator>vigneshvasudeva</dc:creator>
      <dc:date>2014-06-19T12:57:16Z</dc:date>
    </item>
    <item>
      <title>Re: I.MX6Q MIPI-CSI2 voltage level</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/I-MX6Q-MIPI-CSI2-voltage-level/m-p/321708#M42959</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Vignesh&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;yes, your &lt;SPAN style="color: #1f497d;"&gt;understanding is correct. &lt;SPAN style="color: #1f497d;"&gt;MIPI-CSI2 devices will&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #1f497d;"&gt;work with each other well.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;&lt;P&gt;chip&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;P&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 26 Jun 2014 00:13:55 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/I-MX6Q-MIPI-CSI2-voltage-level/m-p/321708#M42959</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2014-06-26T00:13:55Z</dc:date>
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