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    <title>topic Re: parallel port 1 on i.mx6 Dual-lite in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/parallel-port-1-on-i-mx6-Dual-lite/m-p/321517#M42923</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;meaning was not use second IPU.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 29 Jan 2015 01:01:17 GMT</pubDate>
    <dc:creator>igorpadykov</dc:creator>
    <dc:date>2015-01-29T01:01:17Z</dc:date>
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      <title>parallel port 1 on i.mx6 Dual-lite</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/parallel-port-1-on-i-mx6-Dual-lite/m-p/321512#M42918</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Can the parallel port 1 be used on the iMX6 Dual-Lite (&amp;amp; solo)&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Most of the documentation shows that the IPU can accept both Parallel Port #0 &amp;amp; Parallel Port #1&lt;BR /&gt;(e.g. IMX6SDLRM rev 2)&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;However, AN4397 (Common Hardware Design for i.MX 6Dual/6Quad and i.MX 6Solo/6DualLite) Rev 1, contains the rather worrying note:&lt;/P&gt;&lt;P&gt;"NOTE&lt;/P&gt;&lt;P&gt;Do not use Parallel 1 port as the video input when migrating an&lt;/P&gt;&lt;P&gt;i.MX 6Dual/6Quad hardware design to the i.MX 6Solo/6DualLite."&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;(In Chapter 8 Video input requirements for migration)&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;So, what is the reason for this?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;If parallel port 1 cannot be used, then why is it mentioned in all the other documentation?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Phil&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 17 Jul 2014 12:06:53 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/parallel-port-1-on-i-mx6-Dual-lite/m-p/321512#M42918</guid>
      <dc:creator>phil_martin</dc:creator>
      <dc:date>2014-07-17T12:06:53Z</dc:date>
    </item>
    <item>
      <title>Re: parallel port 1 on i.mx6 Dual-lite</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/parallel-port-1-on-i-mx6-Dual-lite/m-p/321513#M42919</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Philip&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;AN4397 tried to convey the fact that i.MX 6Solo/6DualLite have&lt;/P&gt;&lt;P&gt;one IPU module (i.MX 6Dual/6Quad have two IPU modules).&lt;/P&gt;&lt;P&gt;Each IPU have two (CSI0,CSI1) parallel camera ports.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;&lt;P&gt;chip&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;P&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 17 Jul 2014 14:26:38 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/parallel-port-1-on-i-mx6-Dual-lite/m-p/321513#M42919</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2014-07-17T14:26:38Z</dc:date>
    </item>
    <item>
      <title>Re: parallel port 1 on i.mx6 Dual-lite</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/parallel-port-1-on-i-mx6-Dual-lite/m-p/321514#M42920</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Ok, so, I want to input video on both camera ports simultaneously, @1080i/60&lt;/P&gt;&lt;P&gt;- is this possible on the Dual-Lite?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;As far as I can tell, a single IPU can handle 2 video streams simultaneously&lt;/P&gt;&lt;P&gt;- so using the two parallel ports simultaneously should be ok, I think&lt;/P&gt;&lt;P&gt;- do you agree?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Phil&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 17 Jul 2014 14:49:57 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/parallel-port-1-on-i-mx6-Dual-lite/m-p/321514#M42920</guid>
      <dc:creator>phil_martin</dc:creator>
      <dc:date>2014-07-17T14:49:57Z</dc:date>
    </item>
    <item>
      <title>Re: parallel port 1 on i.mx6 Dual-lite</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/parallel-port-1-on-i-mx6-Dual-lite/m-p/321515#M42921</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Philip&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;yes, this is possible.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;&lt;P&gt;chip&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 17 Jul 2014 14:58:58 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/parallel-port-1-on-i-mx6-Dual-lite/m-p/321515#M42921</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2014-07-17T14:58:58Z</dc:date>
    </item>
    <item>
      <title>Re: parallel port 1 on i.mx6 Dual-lite</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/parallel-port-1-on-i-mx6-Dual-lite/m-p/321516#M42922</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Why is this comment in AN4397?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;"Do not use Parallel 1 port as the video input when migrating an&lt;/P&gt;&lt;P&gt;i.MX 6Dual/6Quad hardware design to the i.MX 6Solo/6DualLite."&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;If the DL does have two parallel ports, why is it recommended not to use one?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Randy Krakora&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 29 Jan 2015 00:42:39 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/parallel-port-1-on-i-mx6-Dual-lite/m-p/321516#M42922</guid>
      <dc:creator>RandyKrakora</dc:creator>
      <dc:date>2015-01-29T00:42:39Z</dc:date>
    </item>
    <item>
      <title>Re: parallel port 1 on i.mx6 Dual-lite</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/parallel-port-1-on-i-mx6-Dual-lite/m-p/321517#M42923</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;meaning was not use second IPU.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 29 Jan 2015 01:01:17 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/parallel-port-1-on-i-mx6-Dual-lite/m-p/321517#M42923</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2015-01-29T01:01:17Z</dc:date>
    </item>
    <item>
      <title>Re: parallel port 1 on i.mx6 Dual-lite</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/parallel-port-1-on-i-mx6-Dual-lite/m-p/321518#M42924</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Seems like it should be clarified, because our customer ( and us as well ) assumed it meant you could only use one parallel port on imx6dl. But when we looked at the RM, there were two parallel ports.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I think it should be eliminated from the guide, if you can use both parallel camera ports and/or mipi camera port at the same time on imx6dl.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Can imx6s or dl support three cameras? Either two parallel and one mipi or three mipi, etc. whatever the combination, since it looks to only support two virtual channels? &lt;A _jive_internal="true" class="jiveTT-hover-user jive-link-profile-small" data-containerid="-1" data-containertype="-1" data-content-finding="Community" data-objectid="2014" data-objecttype="3" href="https://community.nxp.com/people/rogeriopimentel"&gt;rogeriopimentel&lt;/A&gt;&lt;SPAN style="color: #222222; font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif; background-color: #ffffff;"&gt; &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;Regrads,&lt;/P&gt;&lt;P&gt;Randy Krakora&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 29 Jan 2015 01:12:53 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/parallel-port-1-on-i-mx6-Dual-lite/m-p/321518#M42924</guid>
      <dc:creator>RandyKrakora</dc:creator>
      <dc:date>2015-01-29T01:12:53Z</dc:date>
    </item>
    <item>
      <title>Re: parallel port 1 on i.mx6 Dual-lite</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/parallel-port-1-on-i-mx6-Dual-lite/m-p/321519#M42925</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Randall,&lt;/P&gt;&lt;P&gt;Let me clarify with R&amp;amp;D. I'll contact you asap.&lt;/P&gt;&lt;P&gt;Rogerio&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 29 Jan 2015 17:09:30 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/parallel-port-1-on-i-mx6-Dual-lite/m-p/321519#M42925</guid>
      <dc:creator>rogerio_silva</dc:creator>
      <dc:date>2015-01-29T17:09:30Z</dc:date>
    </item>
    <item>
      <title>Re: parallel port 1 on i.mx6 Dual-lite</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/parallel-port-1-on-i-mx6-Dual-lite/m-p/321520#M42926</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Randy,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Both parallel ports can be used on i.MX6DL since there are no pin conflicts with other peripherals. The note on application note is just a recommendation to maintain compatibility between the i.MX6Q and i.MX6S design (pin to pin compatibility).&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;By the SoC perspective, i.MX6DL can only support 2 cameras at the same time. The current Freescale BSP doesn't support both cameras at the same time. It must be implemented on IPU/CSI driver.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best Regards,&lt;/P&gt;&lt;P&gt;Rogerio&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 04 Feb 2015 16:25:15 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/parallel-port-1-on-i-mx6-Dual-lite/m-p/321520#M42926</guid>
      <dc:creator>rogerio_silva</dc:creator>
      <dc:date>2015-02-04T16:25:15Z</dc:date>
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