topic Re: i.MX6 SDMA usage in i.MX Processors

i.MX6 SDMA usage

Aemj — Mon, 16 Jun 2014 07:57:57 GMT

Hi all,

I would like to ask about SDMA of i.MX6.

My customer wants to use SDMA with SSI as below.

(1)

DMA transferring from Buffer1(memory) to SSI with specific data size.

(2)

Continuously to completion of (1), start DMA transferring from Buffer2(memory) to SSI with specific data size.

(3)

Continuously to completion of (2), Back to (1).

The customer believes that continuous data transfer to SSI will be achieved by the above procedure.

Is it possible to use SDMA of i.MX6 as above?

Is yes, please let me know how one can handle SDMA for that.

Thanks,

Miyamoto

igorpadykov — Tue, 17 Jun 2014 04:58:26 GMT

Hi avnet japan fae

unfortunately I think not. Though

SDMA transfers can be chained, SDMA processes one

buffer descriptor and then immediately processes the next

buffer descriptor, creating a buffer descriptor chain.

One channel can support up to 64 buffer descriptors in the

chain. After all buffer descriptors are processed one will have

to reinitialize process. Buffer descriptors are described in

iMX6_Firmware_Guide.pdf, included in SDK

Best regards

chip

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Aemj — Fri, 20 Jun 2014 02:16:32 GMT

hi Chipexpert,

Thanks, the customer will try to implement as the SDMA chain.

We can close this.