<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Freescale iMX537 memory question in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Freescale-iMX537-memory-question/m-p/318349#M42285</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt; font-family: 'Calibri','sans-serif';"&gt;Our Freescale iMX537 is connected to flash memory.&amp;nbsp; Sometimes if we corrupt the flash memory, we can’t assert control of the iMX537 with a debugger. If we change the boot&amp;nbsp; mode to serial instead of flash, the processor will at least talk to the debugger, but flash looks like non CFI compliant part.&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; So far the only way we have found to get around this is by removing and replacing the flash chip,&amp;nbsp; but we shouldn’t have to.&amp;nbsp; We should be able to just erase the flash and start over.&amp;nbsp;&amp;nbsp;&amp;nbsp; I can provide details about the flash chip, but the processor should have total control over it, it’s just flash.&amp;nbsp; Is there any insight someone can provide us? Or has anyone run into this before?&amp;nbsp;&amp;nbsp; Is there some register that is getting set in the iMX that would cause flash not to be recognized?&amp;nbsp; (We are not using the fuse settings, we configure the chip with external resistors).&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 12 Jun 2014 19:14:47 GMT</pubDate>
    <dc:creator>Chicago1984</dc:creator>
    <dc:date>2014-06-12T19:14:47Z</dc:date>
    <item>
      <title>Freescale iMX537 memory question</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Freescale-iMX537-memory-question/m-p/318349#M42285</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt; font-family: 'Calibri','sans-serif';"&gt;Our Freescale iMX537 is connected to flash memory.&amp;nbsp; Sometimes if we corrupt the flash memory, we can’t assert control of the iMX537 with a debugger. If we change the boot&amp;nbsp; mode to serial instead of flash, the processor will at least talk to the debugger, but flash looks like non CFI compliant part.&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; So far the only way we have found to get around this is by removing and replacing the flash chip,&amp;nbsp; but we shouldn’t have to.&amp;nbsp; We should be able to just erase the flash and start over.&amp;nbsp;&amp;nbsp;&amp;nbsp; I can provide details about the flash chip, but the processor should have total control over it, it’s just flash.&amp;nbsp; Is there any insight someone can provide us? Or has anyone run into this before?&amp;nbsp;&amp;nbsp; Is there some register that is getting set in the iMX that would cause flash not to be recognized?&amp;nbsp; (We are not using the fuse settings, we configure the chip with external resistors).&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 12 Jun 2014 19:14:47 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Freescale-iMX537-memory-question/m-p/318349#M42285</guid>
      <dc:creator>Chicago1984</dc:creator>
      <dc:date>2014-06-12T19:14:47Z</dc:date>
    </item>
    <item>
      <title>Re: Freescale iMX537 memory question</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Freescale-iMX537-memory-question/m-p/318350#M42286</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Shahzad,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;for jtag connection with i.MX53 (and other i.MX processors)&lt;/P&gt;&lt;P&gt;Freescale recommends only USB/UART mode (other modes connection may be &lt;/P&gt;&lt;P&gt;unreliable), reason explained below :&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;A class="jive-link-external-small" href="http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.faqs/ka11528.html"&gt;http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.faqs/ka11528.html&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Some i.MX processors have special boot mode for jtag connection,&lt;/P&gt;&lt;P&gt;for example i.MX28.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;&lt;P&gt;chip&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;P&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 17 Jun 2014 05:09:16 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Freescale-iMX537-memory-question/m-p/318350#M42286</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2014-06-17T05:09:16Z</dc:date>
    </item>
  </channel>
</rss>

