<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>i.MX ProcessorsのトピックIRQ stack placed in DDR using IMX6SL</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/IRQ-stack-placed-in-DDR-using-IMX6SL/m-p/317485#M42074</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;SPAN style="color: #1f497d;"&gt;Hello community,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #1f497d;"&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #1f497d;"&gt;Our board is crashing after boot-up and when the code starts accessing the EIM bus. This happens the moment that interrupts are enabled. The team believes that the information that is coming back on the EIM bus is corrupting the IRQ stack memory. &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;We don’t have this issue on the eval board that is using a imx6sl. That eval board uses a different chip that has the GPU and EPDC (MCIMX6L8DVN10AB). Our board that uses imx6sl that has no EPDC unit (MCIMX6L3DVN10AB).&amp;nbsp; Is there anything that we should know about the two devices that might affect the EIM of the processor when there is no EPDC? Any tips on solving this issue would be appreciated. &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The OS is eCOS.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Message was edited by: Joshua Parrish&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 09 Jul 2014 02:05:52 GMT</pubDate>
    <dc:creator>jparrish88</dc:creator>
    <dc:date>2014-07-09T02:05:52Z</dc:date>
    <item>
      <title>IRQ stack placed in DDR using IMX6SL</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IRQ-stack-placed-in-DDR-using-IMX6SL/m-p/317485#M42074</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;SPAN style="color: #1f497d;"&gt;Hello community,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #1f497d;"&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #1f497d;"&gt;Our board is crashing after boot-up and when the code starts accessing the EIM bus. This happens the moment that interrupts are enabled. The team believes that the information that is coming back on the EIM bus is corrupting the IRQ stack memory. &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;We don’t have this issue on the eval board that is using a imx6sl. That eval board uses a different chip that has the GPU and EPDC (MCIMX6L8DVN10AB). Our board that uses imx6sl that has no EPDC unit (MCIMX6L3DVN10AB).&amp;nbsp; Is there anything that we should know about the two devices that might affect the EIM of the processor when there is no EPDC? Any tips on solving this issue would be appreciated. &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The OS is eCOS.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Message was edited by: Joshua Parrish&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 09 Jul 2014 02:05:52 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IRQ-stack-placed-in-DDR-using-IMX6SL/m-p/317485#M42074</guid>
      <dc:creator>jparrish88</dc:creator>
      <dc:date>2014-07-09T02:05:52Z</dc:date>
    </item>
    <item>
      <title>Re: Interrupt stack placed in IRAM using IMX6SL</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IRQ-stack-placed-in-DDR-using-IMX6SL/m-p/317486#M42075</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi jparrish88&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I do not think that problem is caused by IRAM.&lt;/P&gt;&lt;P&gt;IRAM is identical for both options of i.MX6SL, problem&lt;/P&gt;&lt;P&gt;may be caused by DDR, since (surely) new calibration&lt;/P&gt;&lt;P&gt;settings should be obtained from links below and used for&lt;/P&gt;&lt;P&gt;each processor differently. Also in code you should check&lt;/P&gt;&lt;P&gt;that there are no references to GPU and EPDC, if they are not persent&lt;/P&gt;&lt;P&gt;in one of these chips.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;A class="jive-link-message-small" data-containerid="2004" data-containertype="14" data-objectid="331721" data-objecttype="2" href="https://community.freescale.com/message/331721#331721"&gt;https://community.freescale.com/message/331721#331721&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;A class="jive-link-wiki-small" data-containerid="32294" data-containertype="2020" data-objectid="96412" data-objecttype="102" href="https://community.freescale.com/docs/DOC-96412"&gt;https://community.freescale.com/docs/DOC-96412&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;&lt;P&gt;chip&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;P&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 10 Jul 2014 02:14:06 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IRQ-stack-placed-in-DDR-using-IMX6SL/m-p/317486#M42075</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2014-07-10T02:14:06Z</dc:date>
    </item>
  </channel>
</rss>

