LPDDR2 pin swapping on iMx6DL

sebp20 — Wed, 11 Jun 2014 08:27:39 GMT

Hi,

i am designing an board with a iMx6DL with 2 LPDDR2 (MT42L256M32D2) chips.

I noticed the LPDDR2 and DRAM pin mux mapping on page 3828 in the TRM.

Is bit swapping allowed on the data lines for easy pcb routing? Which are the restrictions?

Thanks

Sebastian

Re: LPDDR2 pin swapping on iMx6DL

Yuri — Wed, 11 Jun 2014 08:52:32 GMT

Strictly speaking, JEDEC provides pad sequence standardization for LPDDR2 :

Ordering of DQ bits shall be maintained in the system, including within the

package and on the PCB. DQ byte swapping and DQ bit Swapping are not allowed in

the system.

And MCIMX6SLEVK design follows such approach. In the same time i.MX53 design

with LPDDR2 does not : byte and bit within byte swapping is applied there.

Have a great day,
Yuri

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LPDDR2 pin swapping on iMx6DL

Re: LPDDR2 pin swapping on iMx6DL