topic IMX6D ODT in i.MX Processors

IMX6D ODT

tomsaluzzo — Sun, 06 Jul 2014 13:35:39 GMT

Customer is using their controller card, in which they created by copying the schematic and code from MCIMX6Q-SDB. They did not copy the PCB design/layout. In review of the memory ODT, they have the following questions:

Is there a preferred value for the ODT resistance Rtt_non (ie 60 Ohms or 120 Ohms)?

U-Boot sets the nominal ODT resistance value for a write access to 60 Ohms. However, U-Boot sets the Dynamic ODT resistance value to 120 Ohms for burst write accesses. Why is there a different ODT resistance value for a burst write access?

U-Boot sets the system up such that the ODT resistors are enabled in the DDR3 SDRAM’s whenever the IMX6 is writing data to the DDR3 SDRAM’s. U-Boot uses the ODT control pin to disable the ODT resistors in the DDR3 SDRAM’s when reading data out of the SDRAM’s. This makes sense to me; the termination resistors are on the receiving side of the transaction. My question is: Are the ODT termination resistors enabled in the IMX6 when the IMX6 is reading data out of the DDR3 SDRAM’s? If so, how is this accomplished?

There is a Pad Group Control Register at address 0x020E_0774 that sets the input mode of the DDR3 SDRAM data bus signals. U-Boot writes 0x0002_0000 to this register. This configures the DDR3 SDRAM data bus signals for the “differential input mode”. Since the DDR3 SDRAM data bus signals are single ended, I changed the contents of this register to 0x0000_0000. This configures the DDR3 SDRAM data bus signals for the “CMOS input mode”. The board wouldn’t boot after I made this change. Why?

I attempted to write 0x0000_0200 to the Pad Group Control Registers located at the following addresses:

0x020E_754, 0x020E_75C, 0x020E_760, 0x020E_764, 0x020E_76C, 0x020E_778, 0x020E_77C, 0x020E_780.

Writing 0x0000_0200 to these registers sets the ODT resistance value for the DDR3 SDRAM Data Bus (DDR3_SDRAM_D63 – DDR3_SDRAM_D0) to 60 Ohms. Writing 0x0000_0200 to these registers breaks the board (i.e. the board won’t boot). The default (i.e. reset) value for these registers is 0x0000_0000 (ODT resistance disabled). However, when I tried writing 0x0000_0000 to these registers, I broke the board again. Why is this happening?

Tom Saluzzo

FAE

Arrow Electronics

Re: IMX6D ODT

Yuri — Tue, 08 Jul 2014 06:22:10 GMT

Please look at my comments below.

There are no special considerations regarding the ODT of the i.MX6. It is highly

recommended to use simulation technique for PCB design in order to define if termination

is needed and what are optimal parameters. Also optimal values may be found during

testing / debugging on real board.

You are right, termination is provided on receiver side.

So, for read (by CPU) operation resistors are provided (if configured) by the

CPU on CPU side (internally). For write - the CPU asserts ODT signal to inform

DRAM that memory should provide termination.

It is recommended to use only MMDC_MPODTCTRL register to configure ODT of i.MX6.

As for input mode parameter (DDR_INPUT bit), which may be configured as CMOS or differential.

This configures the voltage level at which the pins senses a transition from logic low to logic high and

vice versa. In differential mode, the pins level transitions are at 50%. In CMOS input mode, the pins level

transitions are at 80% for high and 20 % for low. Different DDR_INPUT options may be used in case of timing

problems in order to improve situation.

Have a great day,
Yuri

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Re: IMX6D ODT

tomsaluzzo — Tue, 08 Jul 2014 18:27:41 GMT

This was copied and pasted from the description of the MMDCx_MPODTCTRL register description in the IMX6 Reference Manual:

“On chip ODT byte3 resistor - This field determines the Rtt_Nom of the on chip ODT byte3 resistor during read accesses.”

Do these ODT resistors get set for the DDR3 Data Bus bits only or do the ODT resistors also get set for the Data Mask and Data Strobe bits?

Tom Saluzzo

Field Application Engineer

Arrow Electronics

1000 Pittsford Victor Rd. 2nd Floor

Pittsford, NY 14534

585.820.2781

tsaluzzo@arrow.com

www.arrow.com <http://www.arrow.com/>

Re: IMX6D ODT

Yuri — Thu, 10 Jul 2014 02:49:16 GMT

I was mistaken last time, the ODT resistors (configured via MMDCx_MPODTCTRL )
are actual for the Data lines, Data Mask and Data Strobe signals.

Have a great day,
Yuri