topic Re: Re: Re: MX6Q+LPDDR2(32bit) boot issue in i.MX Processors

MX6Q+LPDDR2(32bit) boot issue

raymondwang — Fri, 06 Jun 2014 02:45:43 GMT

As I mentioned in some threads, we are trying on MX6Q+LPDDR2 combined design. but make no sense why boot failure in mfg bootimage.

We use Mx6DQSDL LPDDR2 Script Aid V0.04.xlsx to generate flashheader DCD part (attached file 6q_lpddr2_32.inc). The Samsung eMCP

DS attched,too.

Our DDR config:

Single Channel 32bit

2CS, each cs is 128Mx32 (totally 1GB)

With default DSE 40ohm (SI configuration in Mx6DQSDL LPDDR2 Script Aid V0.04.xlsx ), 400MHz DDR stress test failure, but it's okay change them

to 34ohm. But with this stress pass DCD, my uboot_mfg can't boot properly (no output in default console).

Please help us!

Original Attachment has been moved to: 6q_lpddr2_32.inc.zip

Original Attachment has been moved to: mx6q_tdh_lpddr2_400_v004.inc.zip

Re: MX6Q+LPDDR2 boot issue

igorpadykov — Fri, 06 Jun 2014 10:25:41 GMT

Hi Raymond

suggest to build just Uboot (not MFG) and try to boot it,

flash_header.S should be modified with new DCD settings.

Regarding MFG Tool, its firmware (initramfs.cpio.gz.uboot)

should be rebuilt with new DCD, please check

i.MX_6Dual6Quad_SABRE-SD_Linux_User's_Guide.pdf

sect.3.9 "Building Manufacturing Firmware".

L3.0.35_4.1.0_LINUX_DOCS

Actually you can download just modified Uboot with MFG Tool,

modifiy ucl2.xml (also one can create new Profile, check with MFG2 Tool documentation).

u-boot-mx6q-sabresd_nopad.bin is Uboot image without offset (0x400).

Note, for USB loading one needs the same images, but without offset.

Changed "SabreSD-SD" profile:

<CMD state="BootStrap" type="boot" body="BootStrap" file ="u-boot-mx6q-sabresd_nopad.bin" >Loading image</CMD>

<CMD state="BootStrap" type="jump" > Jumping to image. </CMD>

</LIST>

On Windows platform for creating Uboot image without offset, "dd"

utility may be used (http://www.chrysocome.net/dd):

dd.exe if=u-boot-mx6q-sabresd.bin of=u-boot-mx6q-sabresd_nopad.bin bs=1024 skip=1

Best regards

chip

Re: MX6Q+LPDDR2 boot issue

raymondwang — Fri, 06 Jun 2014 11:23:18 GMT

Dear igorpadykov

1.I use different profile to test my mfg uboot.

<CMD state="BootStrap" type="boot" body="BootStrap" file ="u-boot-mx6q-tdh-lpddr2_nopad.bin" >Loading U-boot</CMD>

<CMD state="BootStrap" type="jump" > Jumping to OS image. </CMD>

</LIST>

2.Following your instruction, I cut first 1k bytes of my mfg uboot

dd if=u-boot-mx6q-tdh-lpddr2.bin of=u-boot-mx6q-tdh-lpddr2_nopad.bin bs=1024 skip=1

142+1 records in

142+1 records out

146332 bytes (146 kB) copied, 0.00187831 s, 77.9 MB/s

Still there is no message output in uart console.

Re: MX6Q+LPDDR2 boot issue

raymondwang — Fri, 06 Jun 2014 11:28:35 GMT

I also have a double check on existed mfg u-boot-mx6q-sabresd.bin. It contains first 1k padding bytes.

Re: MX6Q+LPDDR2 boot issue

igorpadykov — Fri, 06 Jun 2014 11:31:38 GMT

Hi Raymond

could you try to rebuild just Linux Uboot

(not Android) and try ?

L3.0.35_4.1.0_ER_SOURCE_BSP

Actually does board output anything ?

Did you try SDK ?

i.MX 6Series Platform SDK :

Best regards

chip

Re: MX6Q+LPDDR2 boot issue

raymondwang — Fri, 06 Jun 2014 11:35:54 GMT

Actually, there is nothing output in uart1 (1st uart). Are you sure that rebuild uboot source useful?

Re: MX6Q+LPDDR2 boot issue

igorpadykov — Sat, 07 Jun 2014 14:53:15 GMT

Hi Raymond

suggest to start with SDK and oscilloscope

i.MX 6Series Platform SDK :

Best regards

chip

Re: MX6Q+LPDDR2(32bit) boot issue

raymondwang — Sun, 08 Jun 2014 06:50:01 GMT

Dear chipexpert,

Thanks for your response! I checked iMX6 platform sdk, it does not contains LPDDR2 single channel DCD for MX6Q series boards.

MX6Q EVB ->2GB DDR3 @64bit single channel

MX6Q Sabre_ai ->DDR3

MX6Q Sabre_SmartDevice ->DDR3

I don't have JTAG tool,therefore I have to fix my DCD for DDR initialization issue.

BTW,my board DDR signal is routed in inner layer. Probably routing not good enough, we can't run memory stress test pass in 432MHz or

above.

My question is , DDR stress test pass in 400MHz, Why it fails to bringup LPDDR2 using same DCD config?

RaymondW

Re: MX6Q+LPDDR2(32bit) boot issue

igorpadykov — Sun, 08 Jun 2014 15:40:12 GMT

Hi Raymond

you can add to DCD (and Uboot) code to set some GPIO,

then check where code hangs.

Best regards

chip

Re: MX6Q+LPDDR2(32bit) boot issue

raymondwang — Mon, 09 Jun 2014 01:40:01 GMT

Dear Chip

I tried to enable 1 gpio to light on a LED, seems failure . I think this means cpu did not

run there.

BTW, I found a DCD data to enable DDR 400MHz:

setmem /32 0x020c4018 = 0x00060324

Is it right?

RaymondWang

Re: MX6Q+LPDDR2(32bit) boot issue

igorpadykov — Mon, 09 Jun 2014 03:55:48 GMT

Hi Raymond

suggest to verify that GPIO module clock is not

gated in CCM registers (CCM_CCGR).

Best regards

chip

Re: MX6Q+LPDDR2(32bit) boot issue

raymondwang — Mon, 09 Jun 2014 04:07:01 GMT

I Add the gpio code in uboot since DCD can't access gpio module directly.

I test my uboot with sabresd DDR3 config, it does work.

Only one CCM register is set in DCD,

setmem /32 0x020c4018 = 0x00060324

I don't think it relevant to GPIO required clocks.

I doubt DCD ccm register setting not enough to let LPDDR2 working at 400MHz. Our board

can't pass 528MHz DDR stress test.

Re: MX6Q+LPDDR2 boot issue

igorpadykov — Mon, 09 Jun 2014 08:07:14 GMT

Hi Raymond

you can try other settings as below

iMX6DQ LPDDR2 Initialization Issue

Best regards

chip

Re: MX6Q+LPDDR2(32bit) boot issue

raymondwang — Mon, 09 Jun 2014 08:43:05 GMT

I tried ,same behavior as before. and that init script is 533MHz, running DDR stress test will fail.

Re: MX6Q+LPDDR2(32bit) boot issue

igorpadykov — Mon, 09 Jun 2014 09:23:06 GMT

Hi Raymond

what BSP are you using ?

What documents (if any) are you reading when

preparing images ?

Best regards

chip

Re: MX6Q+LPDDR2(32bit) boot issue

raymondwang — Mon, 09 Jun 2014 09:36:28 GMT

my bsp is Android4.2.2-1.1.0-GA And my board design is based on SabreSD ( but using different DDR and PMIC).

Mine is LPDD2 and PMIC is PF0100F1 (specially for LPDDR2 application)

Re: MX6Q+LPDDR2(32bit) boot issue

igorpadykov — Mon, 09 Jun 2014 09:45:09 GMT

Hi Raymond

I would suggest to use Linux or even SDK

at bring-up phase. They are simpler, better documented,

easier for debugging.

L3.0.35_4.1.0_ER_SOURCE_BSP

i.MX 6Series Platform SDK

Best regards

chip

Re: MX6Q+LPDDR2(32bit) boot issue

raymondwang — Mon, 09 Jun 2014 10:31:05 GMT

I am not familiar on linux or mx6 SDK. But I reviewed sdk source tree, no instinct difference between SDK and UBOOT stand for

board dcd configuration.

Re: Re: MX6Q+LPDDR2(32bit) boot issue

raymondwang — Tue, 10 Jun 2014 04:15:12 GMT

I rebuild sdk_unit_test_ALL.bin with replacing smart_device dcd.c to my LPDDR2.

And add it to mfg tool

<CMD state="BootStrap" type="boot" body="Recovery" file="sdk_unit_test_ALL.bin">Loading

SDK image</CMD>

<CMD state="BootStrap" type="jump">Jumping to SDK image.</CMD>

</LIST>

The mfgtool hangs with display state in "Loading SDK image" about 75% over 5mins.

I enclosed my new dcd.c.

Re: Re: Re: MX6Q+LPDDR2(32bit) boot issue

igorpadykov — Tue, 10 Jun 2014 07:33:08 GMT

Hi Raymond

I would suggest to start

with attached examples. One uses iRAM,

second DDR3 - you can modify it for LPDDR2.

Optionally you can build SDK examples and run in iRAM using link below

iRAM (OCRAM) i.MX6 SDK Application

Best regards

chip