i.MX ProcessorsのトピックRe: Questions about value in reg MMDC1_MDASP.

Questions about value in reg MMDC1_MDASP.

simmisxu — Thu, 05 Jun 2014 06:50:20 GMT

Hi ALL,

MMDC1_MDASP defines partioning between DDR CS0&CS1.

The sabre ai board is 2G DDR with only CS0. I think the section CS0_END in MMDC1_MDASP should be 011_1111. But the actual value in flash_header.S is 100_0111,

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MXC_DCD_ITEM(71, MMDC_P0_BASE_ADDR + 0x040, 0x00000047)

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I wonder what's the meaning of 100_0111, which is no listed in RM.

Thanks,

Simmis.

Re: Questions about value in reg MMDC1_MDASP.

Yuri — Thu, 05 Jun 2014 07:49:22 GMT

Hope the following considerations help :

Chan0 start addr = 0x1000_0000 ; density_MB_per_CS = 0x8000_0000

Chan0 CS0_END [(Chan0_start_addr + density_MB_per_CS) / 0x0200_0000] – 1 = 0x47

Have a great day,
Yuri

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Re: Questions about value in reg MMDC1_MDASP.

simmisxu — Thu, 05 Jun 2014 09:12:49 GMT

Hi Yuri,

Thanks for your quick reply.

May I know the background of "dividing 0x0200_0000"

Thanks,

Simmis.

Re: Questions about value in reg MMDC1_MDASP.

Yuri — Thu, 05 Jun 2014 09:20:22 GMT

From the register description : "Defines the absolute last address associated with CS0 with increments of 256Mb".

0x0200_0000 = 256Mb

Have a great day,
Yuri

Re: Questions about value in reg MMDC1_MDASP.

simmisxu — Thu, 05 Jun 2014 10:09:26 GMT

Got it! According to this, I think values in RM are wrong.

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CS0_END. Defines the absolute last address associated with CS0 with increments of 256Mb.

CS0_END=AXI_ADDRESS[31:25] bits.

000_0000 256Mb

000_0001 512Mb

001_1111 8Gb (1GB)

011_1111 16Gb (2GB) - default

111_1111 32Gb (4GB)

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Re: Questions about value in reg MMDC1_MDASP.

Yuri — Fri, 06 Jun 2014 04:18:15 GMT

CS0_END description in the RM does not mention about base address and provides only offsets.