IMX6Q processor Pin Delay considerations

vinodkumar — Tue, 01 Jul 2014 13:22:25 GMT

Hi all,

We are referring below reference design link for our project.

In this Design Board file constraint manager, Pin delay is included for calculating total trace length.

Please let us know answer for below queries

1. we should consider pin delay for calculating total trace length?

2. What is the processor pin delay for Data, command & control pins?

3. Whether we should consider DDR3 SDRAM chip pin delays? We are using MT41J256M16RE-15E:D in our design. what will be pin delay?

Re: IMX6Q processor Pin Delay considerations

Yuri — Wed, 02 Jul 2014 01:20:02 GMT

Usually we do not provide information about internal traces. Actually customers can

ignore the lengths of internal bonding wires as they are really very short.
For simulation, customers only needs to consider signals trace length on PCB.
Let me remind, IBIS model includes internal traces and general approach is just to follow

requirements of the design checklist and PCB layout recommendations, for example, provided

in the "Hardware Development Guide for i.MX 6 ...".

Have a great day,
Yuri

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topic Re: IMX6Q processor Pin Delay considerations in i.MX Processors

IMX6Q processor Pin Delay considerations

Re: IMX6Q processor Pin Delay considerations