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    <title>i.MX ProcessorsのトピックRe: iMX25 DDR2 layout inquiry:</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/iMX25-DDR2-layout-inquiry/m-p/314155#M41250</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Basically, the best approach - to use simulation technique for PCB design.&lt;/P&gt;&lt;P&gt;In the same time, general rules may be provided for customers to simplify their &lt;/P&gt;&lt;P&gt;PCB considerations, but note, for assurance such rules are very strong.&lt;/P&gt;&lt;P&gt;&amp;nbsp; So, if You can simulate the PCB design please use it, if cannot - please follow &lt;/P&gt;&lt;P&gt;general (and more strong) recommendations. To avoid signal overshooting, please&lt;/P&gt;&lt;P&gt;try to apply different drive strength options for both i.MX25 and DDR2 part. In particular, &lt;/P&gt;&lt;P&gt;section 1.3 (Calculating the Characteristic Impedance) of app note AN3963 shows how to &lt;/P&gt;&lt;P&gt;estimate it. Also one can apply to JEDEC recommendations for DIMM / SODIMM (termination) &lt;/P&gt;&lt;P&gt;schemes.&lt;/P&gt;&lt;P&gt;&amp;nbsp; Finally, please refer to section 3 (mDDR and DDR2 Routing Guidelines) of AN4017.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Below are app note links :&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;A class="moz-txt-link-rfc2396E" href="http://cache.freescale.com/files/dsp/doc/app_note/AN3963.pdf"&gt;&lt;/A&gt;&lt;A href="http://cache.freescale.com/files/dsp/doc/app_note/AN3963.pdf" target="test_blank"&gt;http://cache.freescale.com/files/dsp/doc/app_note/AN3963.pdf&lt;/A&gt; &lt;BR /&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;A class="moz-txt-link-rfc2396E" href="http://cache.freescale.com/files/dsp/doc/app_note/AN4017.pdf"&gt;&lt;/A&gt;&lt;A href="http://cache.freescale.com/files/dsp/doc/app_note/AN4017.pdf" target="test_blank"&gt;http://cache.freescale.com/files/dsp/doc/app_note/AN4017.pdf&lt;/A&gt; &lt;BR /&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Have a great day,&lt;BR /&gt;Yuri&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 01 Jul 2014 09:57:39 GMT</pubDate>
    <dc:creator>Yuri</dc:creator>
    <dc:date>2014-07-01T09:57:39Z</dc:date>
    <item>
      <title>iMX25 DDR2 layout inquiry:</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX25-DDR2-layout-inquiry/m-p/314154#M41249</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;on our old iMX25 board(6-layer through whole board), there are 27ohm resistors between iMX25 and DDR2. Are these resistors necessary? can we remove them, our new board size is much smaller? Another question is could we change the DDR2 DATA lines connection order by group? thanks.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 01 Jul 2014 07:50:56 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX25-DDR2-layout-inquiry/m-p/314154#M41249</guid>
      <dc:creator>yuanli</dc:creator>
      <dc:date>2014-07-01T07:50:56Z</dc:date>
    </item>
    <item>
      <title>Re: iMX25 DDR2 layout inquiry:</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX25-DDR2-layout-inquiry/m-p/314155#M41250</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Basically, the best approach - to use simulation technique for PCB design.&lt;/P&gt;&lt;P&gt;In the same time, general rules may be provided for customers to simplify their &lt;/P&gt;&lt;P&gt;PCB considerations, but note, for assurance such rules are very strong.&lt;/P&gt;&lt;P&gt;&amp;nbsp; So, if You can simulate the PCB design please use it, if cannot - please follow &lt;/P&gt;&lt;P&gt;general (and more strong) recommendations. To avoid signal overshooting, please&lt;/P&gt;&lt;P&gt;try to apply different drive strength options for both i.MX25 and DDR2 part. In particular, &lt;/P&gt;&lt;P&gt;section 1.3 (Calculating the Characteristic Impedance) of app note AN3963 shows how to &lt;/P&gt;&lt;P&gt;estimate it. Also one can apply to JEDEC recommendations for DIMM / SODIMM (termination) &lt;/P&gt;&lt;P&gt;schemes.&lt;/P&gt;&lt;P&gt;&amp;nbsp; Finally, please refer to section 3 (mDDR and DDR2 Routing Guidelines) of AN4017.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Below are app note links :&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;A class="moz-txt-link-rfc2396E" href="http://cache.freescale.com/files/dsp/doc/app_note/AN3963.pdf"&gt;&lt;/A&gt;&lt;A href="http://cache.freescale.com/files/dsp/doc/app_note/AN3963.pdf" target="test_blank"&gt;http://cache.freescale.com/files/dsp/doc/app_note/AN3963.pdf&lt;/A&gt; &lt;BR /&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;A class="moz-txt-link-rfc2396E" href="http://cache.freescale.com/files/dsp/doc/app_note/AN4017.pdf"&gt;&lt;/A&gt;&lt;A href="http://cache.freescale.com/files/dsp/doc/app_note/AN4017.pdf" target="test_blank"&gt;http://cache.freescale.com/files/dsp/doc/app_note/AN4017.pdf&lt;/A&gt; &lt;BR /&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Have a great day,&lt;BR /&gt;Yuri&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 01 Jul 2014 09:57:39 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX25-DDR2-layout-inquiry/m-p/314155#M41250</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2014-07-01T09:57:39Z</dc:date>
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