topic Re: PF0100 question in i.MX Processors

PF0100 question

jwu — Sat, 05 Apr 2014 05:33:20 GMT

It looks like the programmer supports in-circuit programming for the MMPF0100. Fig. 4 of KTPFPGMEVMEUG shows that I2C and VIN connections on the MMPF0100 are required. Questions / issues:

1. If the CPU is not powered, will pullups on I2C cause problems on the CPU?

2. VDDIO must be connected to VIN, which is not the normal connection on the board.

Do most customers use the socket to program the MMPF0100, and then solder it on the board? This won't allow testing of the configuration, but it will avoid the issues above.

Re: PF0100 question

jwu — Tue, 08 Apr 2014 05:23:34 GMT

Re: PF0100 question

alfred_liu — Tue, 08 Apr 2014 08:47:34 GMT

Hi, John

the I2C and VIN connections should be designed as optional circuit, they do affect the CPU.

when you program pfuse, you connect the I2C and VIN for pfuse. when you finish the program, you should remove these optional parts (resisters....)

so the the I2C and VIN are only for program and should be optional with resisters.

Re: PF0100 question

alfred_liu — Tue, 08 Apr 2014 08:50:01 GMT

Hi, John

for LDO, I think you can refer to SW, add 0.1uF on the input and leave the output float.

Re: PF0100 question

Yuri — Tue, 08 Apr 2014 09:27:28 GMT

Please refer to Table 1 (MMPF0100 Pin Connection Guidelines) of AN4717

(Schematic Guidelines for the MMPF0100).

http://cache.freescale.com/files/analog/doc/app_note/AN4717.pdf

Re: PF0100 question

jwu — Fri, 11 Apr 2014 16:57:25 GMT

Thanks all for great answers!

I2C is required to program the OTP fuses of the PF0100. When this is done in-circuit, I2C is shared with the CPU. The CPU will not be powered, but I2C will be pulled up to 3.3V through 10K resistors, while NVCC_GPIO is at 0V. Can this damage the I2C pins on the CPU, or will the 10K resistors limit the current sufficiently to be prevent damage?

Populating and depopulating resistors to program the PF0100 is not a very good solution: it will slow down production, and is mistake-prone.

Re: PF0100 question

jwu — Sun, 13 Apr 2014 22:41:12 GMT

3. Section 4.9.1 of IMX6SDLIEC: SRC_POR_B rise and fall times must be 5ns or less.

POR_B has an internal 100K pullup, and the Sabre design does not have any additional pullups. POR_B is driven by an open-drain output on the PMIC. Even with a board and pin capacitance as low as 10pF, the rise time will be 5RC = 5us = 5000ns.

4. The Sabre design uses a pushbutton with a 0.1uF capacitor on the PF0100's PWRON, as a means of resetting the CPU. Is this the best way to do it? It will in effect cycle power, as all power supplies on the PMIC will be turned off and then on again. Why not use POR_B to reset the CPU?

Re: PF0100 question

YixingKong — Fri, 20 Jun 2014 02:49:07 GMT

Weisong

Could you keep following the thread so that we can close the customer's issues?

Thanks,

Yixing

Re: PF0100 question

YixingKong — Mon, 30 Jun 2014 08:00:33 GMT

Weisong

Could you finish the following-up of this customer's issue, or need help from others?

Thanks,

Yixing

Re: PF0100 question

YixingKong — Tue, 15 Jul 2014 05:57:26 GMT

Alfred1z

Please see if you are able to help this customer's request. If you need help from others please let me know.

Thanks,

Yixing

Re: PF0100 question

alfred_liu — Tue, 15 Jul 2014 06:13:50 GMT

Hi, John

from my understanding, this optional circuit is just for test or debug.

for mass production, you can ask FSL programme the chip for you.

Re: PF0100 question

alfred_liu — Tue, 15 Jul 2014 06:22:38 GMT

Hi, John

I believe the "5ns" is a typo in document, I don;t see this information in latest imx6QD document.

Re: PF0100 question

YixingKong — Wed, 30 Jul 2014 07:05:27 GMT

John

Should we close the issue since Weisong replied you already?

Thanks,

Yixing

Re: PF0100 question

YixingKong — Mon, 18 Aug 2014 07:24:47 GMT

John

This discussion is closed since no activity. If you still need help, please feel free to reply with an update to this discussion, or create another discussion.

Thanks,

Yixing