DDR3 clock domain

pscz — Tue, 06 May 2014 13:29:17 GMT

Hello,

I've been working on the hardware of a board with a 4core i.MX6.

I have 4 memory chip, all DDR3.

From the reference design (MCIMX6Q-SMART DEVICE BOARD, pag. 4), I see that:

- two DDR3 modules are connected to DRAM_SDCLK0

- two DDR3 modules are connected to DRAM_SDCLK1

The clock enable used is DRAM_SDCKE0 while DRAM_SDCKE1 is unconnected.

Also DRAM_SDODT0 controls the on-die termination of all the four modules while DRAM_SDODT1 is unconnected.

Can anyone explain why?

Thank you in advance,

Alessandro

Re: DDR3 clock domain

igorpadykov — Wed, 07 May 2014 03:34:26 GMT

Hi alesandro,

on MCIMX6Q-SMART DEVICE BOARD, pag. 4

all 4 memory chip, all DDR3 are connected to DRAM_CS0,

so DRAM_SDCKE1,DRAM_SDODT1 are not used (they are used

with DRAM_CS0). However DRAM_SDCLK0,DRAM_SDCLK1 is the

same signal (duplicates each other).

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