i.MX ProcessorsのトピックRe: LCD TFT interface with IPU

LCD TFT interface with IPU

pscz — Fri, 30 May 2014 15:15:56 GMT

Hi guys,

I'm developing a board based on i.MX6 processor.

I'm at the display interface section.

I need to drive an LCD TFT display on parallel standard bus with 6 bits per color.

Signals: VSYNC, HSYNC, DENABLE, CLK, R0...R5, G0...G5, B0...B5

My concern is about the "color bits".

The document "IMX6DQRM" at pag. 2700 says: "RGB - color depth fully configurable; up to 8 bits/value (color component)"

It means that (for example) I can connect "R2" to one of the "DISP_DATAxx" indiscriminately? In other words: is it only up to the software level to configure the parallel bus interface?

Thank you in advance,

Alessandro Piscozzo

Re: LCD TFT interface with IPU

Yuri — Mon, 02 Jun 2014 01:46:00 GMT

According to the i.MX6 Datasheet (IMX6DQCEC,Rev. 3, 02/2014) :

"The IPU supports a number of display output video formats. Table 68 defines the mapping of the Display

Interface Pins used during various supported video interface formats." But please pay attentions on the next

footnotes of Table 68 :

"Restrictions for ports IPUx_DISPx_DAT00 through IPUx_DISPx_DAT23 are as follows:

• A maximum of three continuous groups of bits can be independently mapped to the external bus. Groups must not overlap.

• The bit order is expressed in each of the bit groups, for example, B[0] = least significant blue pixel bit."

In addition please look at the following post :

https://community.freescale.com/thread/322072

Have a great day,
Yuri

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Re: LCD TFT interface with IPU

pscz — Tue, 03 Jun 2014 08:17:23 GMT

Hi Yuri,

thank you for your answer.

I looked at the post that you reported.

Actually it refers to the document "IMX6SDLCEC" which gives a standard configuration of the RGB pins on the IPU interface.

It gives a particular solution... maybe I'll implement that, but I still don't understand wether the standard solution is further configurable for layout reasons.

I mean... even assuming that the whole bus is fully configurable (which is likely true since the same document says: "Signal mapping (both data and control/synchronization) is flexible. The table provides examples"),

what:

"A maximum of three continuous groups of bits can be independently mapped to the external bus" means?

The document doesn't refere to any of these "group". There is not a precise definition.

I think that for the 18bits configuration: ( G[0]...G[5] ) is a group ( R[0]...R[5] ) is another and ( B[0]...B[5] ) is the last.

If that is true, why anybody should map more that three groups for the RGB standard?

And what the word "continous" refers to?

I'll follow the suggested conofiguration anyway.

Thank you,

Alessandro

Re: LCD TFT interface with IPU

Yuri — Wed, 04 Jun 2014 06:10:40 GMT

"continous" means that, say, the next configuration is NOT enabled (when considering RGB bits mapping in 32-bit world) :
R0..R5 G0..G7 R6 R7 B0..B7