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    <title>topic Re: i.MX6 NAND Timing setting. in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6-NAND-Timing-setting/m-p/307868#M39778</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Satoshi, answers below.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;[Q1]When m_NANDTiming setting is applied?Immediately after reading &lt;/P&gt;&lt;P&gt;FCB?After copy DBBT to iRAM?Or on the time start downloading a boot &lt;/P&gt;&lt;P&gt;loader from NAND?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;A1. m_NANDTiming setting are applied immediately after reading &lt;/P&gt;&lt;P&gt;FCB by iROM.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;[Q2]Some parameter in m_NANDTiming is set by GPMI register too.(e.g. data setup, &lt;/P&gt;&lt;P&gt;data hold, address setup)Then, could you let me know which setting (m_NANDTiming &lt;/P&gt;&lt;P&gt;or GPMI register) is used on each timing? (e.g. boot loader =&amp;gt; mNANDTiming, after &lt;/P&gt;&lt;P&gt;kernel uncompression =&amp;gt; GPMI register)&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;A2. I am not quite sure if I understood well question.&lt;/P&gt;&lt;P&gt;Yes, iROM boot loader uses mNANDTiming, however each application:&lt;/P&gt;&lt;P&gt;Uboot or Linux MTD NAND driver can use own GPMI settings.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;[Q3]I think NAND timing set by m_NANDTiming is not effected even if user &lt;/P&gt;&lt;P&gt;change CCM setting in DCD to rapid NAND access.Because the CCM &lt;/P&gt;&lt;P&gt;setting decides only clock period, and m_NANDTiming does not have the &lt;/P&gt;&lt;P&gt;period setting.Is this correct?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;A3. Yes,&amp;nbsp; m_NANDTiming settings do not have the period setting,&lt;/P&gt;&lt;P&gt;because they define one NAND data access (setup, hold times), &lt;/P&gt;&lt;P&gt;while DCD CCM defines (period) - that is how fast processor core accesses &lt;/P&gt;&lt;P&gt;to NAND. So actually CCM settings in DCD can rapid NAND access.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;&lt;P&gt;chip&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;P&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Fri, 30 May 2014 09:24:36 GMT</pubDate>
    <dc:creator>igorpadykov</dc:creator>
    <dc:date>2014-05-30T09:24:36Z</dc:date>
    <item>
      <title>i.MX6 NAND Timing setting.</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6-NAND-Timing-setting/m-p/307867#M39777</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi community,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I have a question about i.MX6 GPMI and NAND boot.&lt;/P&gt;&lt;P&gt;Our customer want to know how m_NANDTiming of FCB is used for NAND timing setting.&lt;/P&gt;&lt;P&gt;And want to know the relationship between m_NANDTiming and CCM register and GPMI register if CCM register setting is added &lt;SPAN style="font-size: 10pt; line-height: 1.5em;"&gt;to DCD for NAND boot also.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;Actually, the partner add CCM setting in DCD file to rapid NAND access because NAND access on boot sequence was slow.&lt;/P&gt;&lt;P&gt;Then, please see my question as following.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;[Q1]&lt;/P&gt;&lt;P&gt;When m_NANDTiming setting is applied?&lt;/P&gt;&lt;P&gt;Immediately after reading FCB?&lt;/P&gt;&lt;P&gt;After copy DBBT to iRAM?&lt;/P&gt;&lt;P&gt;Or on the time start downloading a boot loader from NAND?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;[Q2]&lt;/P&gt;&lt;P&gt;Some parameter in m_NANDTiming is set by GPMI register too.&lt;/P&gt;&lt;P&gt;(e.g. data setup, data hold, address setup)&lt;/P&gt;&lt;P&gt;Then, could you let me know which setting (m_NANDTiming or GPMI register) is used on each timing?&lt;/P&gt;&lt;P&gt;(e.g. boot loader =&amp;gt; mNANDTiming, after kernel uncompression =&amp;gt; GPMI register)&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;[Q3]&lt;/P&gt;&lt;P&gt;I think NAND timing set by m_NANDTiming is not effected even if user change CCM setting in DCD to rapid NAND access.&lt;/P&gt;&lt;P&gt;Because the CCM setting decides only clock period, and m_NANDTiming does not have the period setting.&lt;/P&gt;&lt;P&gt;Is this correct?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best Regards,&lt;/P&gt;&lt;P&gt;Satoshi Shimoda&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 29 May 2014 01:36:06 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6-NAND-Timing-setting/m-p/307867#M39777</guid>
      <dc:creator>satoshishimoda</dc:creator>
      <dc:date>2014-05-29T01:36:06Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX6 NAND Timing setting.</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6-NAND-Timing-setting/m-p/307868#M39778</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Satoshi, answers below.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;[Q1]When m_NANDTiming setting is applied?Immediately after reading &lt;/P&gt;&lt;P&gt;FCB?After copy DBBT to iRAM?Or on the time start downloading a boot &lt;/P&gt;&lt;P&gt;loader from NAND?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;A1. m_NANDTiming setting are applied immediately after reading &lt;/P&gt;&lt;P&gt;FCB by iROM.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;[Q2]Some parameter in m_NANDTiming is set by GPMI register too.(e.g. data setup, &lt;/P&gt;&lt;P&gt;data hold, address setup)Then, could you let me know which setting (m_NANDTiming &lt;/P&gt;&lt;P&gt;or GPMI register) is used on each timing? (e.g. boot loader =&amp;gt; mNANDTiming, after &lt;/P&gt;&lt;P&gt;kernel uncompression =&amp;gt; GPMI register)&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;A2. I am not quite sure if I understood well question.&lt;/P&gt;&lt;P&gt;Yes, iROM boot loader uses mNANDTiming, however each application:&lt;/P&gt;&lt;P&gt;Uboot or Linux MTD NAND driver can use own GPMI settings.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;[Q3]I think NAND timing set by m_NANDTiming is not effected even if user &lt;/P&gt;&lt;P&gt;change CCM setting in DCD to rapid NAND access.Because the CCM &lt;/P&gt;&lt;P&gt;setting decides only clock period, and m_NANDTiming does not have the &lt;/P&gt;&lt;P&gt;period setting.Is this correct?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;A3. Yes,&amp;nbsp; m_NANDTiming settings do not have the period setting,&lt;/P&gt;&lt;P&gt;because they define one NAND data access (setup, hold times), &lt;/P&gt;&lt;P&gt;while DCD CCM defines (period) - that is how fast processor core accesses &lt;/P&gt;&lt;P&gt;to NAND. So actually CCM settings in DCD can rapid NAND access.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;&lt;P&gt;chip&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;P&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 30 May 2014 09:24:36 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6-NAND-Timing-setting/m-p/307868#M39778</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2014-05-30T09:24:36Z</dc:date>
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