<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>i.MX ProcessorsのトピックSimple Ram interface to imx6Q</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Simple-Ram-interface-to-imx6Q/m-p/307486#M39694</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I was going through some files in the L3.0.35_4.1.0 for accessing the memory connected to the EIM bus as a simple RAM.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I came across mtdram.c and map_ram.c&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Can anyone explain their significance to me and tell me how i can use them to access an SRAM connected to an MX6q on the EIM bus with a chip select&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;regards,&lt;/P&gt;&lt;P&gt;nishad&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 01 Apr 2014 07:35:02 GMT</pubDate>
    <dc:creator>nishad_kamdar</dc:creator>
    <dc:date>2014-04-01T07:35:02Z</dc:date>
    <item>
      <title>Simple Ram interface to imx6Q</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Simple-Ram-interface-to-imx6Q/m-p/307486#M39694</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I was going through some files in the L3.0.35_4.1.0 for accessing the memory connected to the EIM bus as a simple RAM.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I came across mtdram.c and map_ram.c&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Can anyone explain their significance to me and tell me how i can use them to access an SRAM connected to an MX6q on the EIM bus with a chip select&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;regards,&lt;/P&gt;&lt;P&gt;nishad&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 01 Apr 2014 07:35:02 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Simple-Ram-interface-to-imx6Q/m-p/307486#M39694</guid>
      <dc:creator>nishad_kamdar</dc:creator>
      <dc:date>2014-04-01T07:35:02Z</dc:date>
    </item>
    <item>
      <title>Re: Simple Ram interface to imx6Q</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Simple-Ram-interface-to-imx6Q/m-p/307487#M39695</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;As mentioned in&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.nxp.com/thread/321672"&gt;SRAM support on EIM bus existing drivers&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;it makes sense to reuse the WEIM driver, included in i.MX6 Sabre AI design.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Have a great day,&lt;BR /&gt;Yuri&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 02 Apr 2014 10:30:52 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Simple-Ram-interface-to-imx6Q/m-p/307487#M39695</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2014-04-02T10:30:52Z</dc:date>
    </item>
  </channel>
</rss>

