i.MX Processorsのトピックimx6 SDMA and EIM bus

imx6 SDMA and EIM bus

ao1 — Wed, 28 May 2014 11:22:39 GMT

I would like to use external events on the pins event0, and event1 to trigger SDMA requests to send data to the external EIM bus.

I am using IMX_DMATYPE_EXT for configuring the dma, and I use event1 as an external trigger. I have observed that

the events are handled by the DMA, and empties the buffer, but I don't see anything on the EIM bus.

I have started having the impression that the IMX_DMATYPE_EXT is using ROM scripts that do not put data to the EIM bus.

    case IMX_DMATYPE_EXT:
        per_2_emi = sdma->script_addrs->app_2_mcu_addr;
        emi_2_per = sdma->script_addrs->mcu_2_app_addr;
        break;

And as far I can see from the imx6 manual:

mcu_2_app
This generic script is used to transfer data from memories accessed by the BurstDMA
(External memories), to a 8, 16, 24 or 32-bit peripheral connected to the AIPS accessed
through the Periphera DMA of SDMA.

Have you ever had external SDMA events to trigger transfers to EIM bus? It should be possible, right?

Kind regards,

Re: imx6 SDMA and EIM bus

Yuri — Thu, 29 May 2014 02:49:18 GMT

Input signals SDMA_EXT_EVENT0, SDMA_EXT_EVENT1 are used as external
DMA request event signals and are designed to trigger internal DMA transactions.
Please take a look at Table 55-1 (SDMA External Signals) of the i.MX6 DQ RM.

The external request works as an internal request triggered by a FIFO.

We provide (in software) :

- source address of the FIFO (external memory address) ;

- destination address in RAM or wherever ;

- count (total number of bytes to exchange) ;

- burst length (close to the watermark level of the FIFO that triggers the DMA

event).

Then, a DMA event triggers a DMA channel. Depending on the channel priority, but

in most of the case very quickly, an access is done to the external device FIFO

through the WEIM.

Practically the access looks like as usual CPU-related one, at least the

external device cannot distinguish between DMA and CPU ones, because both are

working via the WEIM, and fully defined by WEIM settings.

The selected burst length defines length (duration) of this access.

If the DMA event signal is still asserted, the access will continue with a next

burst, if not - the DMA waits for a next event to do an access.

Indeed, there is no real flow control, but the external peripheral should be

enable to generate some DMA event each time its FIFO has reached a watermark level.

Note, there is no need for external grant / acknowledge signal.

Have a great day,
Yuri

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Re: imx6 SDMA and EIM bus

ao1 — Thu, 29 May 2014 10:26:54 GMT

Thank you for your reply, however I would like a bit more information please

It is not clear from your answer which SDMA scrip to use to perform the DMA transactions.

Some of the FIFO peripherals, like ECSPI, make DMA requests from the Peripheral DMA bus,

and their corresponding SDMA script may have instructions that are different from accessing a FIFO based on on Burst DMA bus.

Simple, in my case I have a buffer in RAM with data, and the FPGA is attached to the EIM bus. The FPGA makes

requests to one of event pins EVENT1 for data. The SDMA should handle the requests and send data out to the FPGA.

Which ROM SDMA scrip do I have to use for the above use case? The available ROM scripts are:

   s32 ap_2_ap_addr;
    s32 ap_2_bp_addr;
    s32 ap_2_ap_fixed_addr;
    s32 bp_2_ap_addr;
    s32 loopback_on_dsp_side_addr;
    s32 mcu_interrupt_only_addr;
    s32 firi_2_per_addr;
    s32 firi_2_mcu_addr;
    s32 per_2_firi_addr;
    s32 mcu_2_firi_addr;
    s32 uart_2_per_addr;
    s32 uart_2_mcu_addr;
    s32 per_2_app_addr;
    s32 mcu_2_app_addr;
    s32 per_2_per_addr;
    s32 uartsh_2_per_addr;
    s32 uartsh_2_mcu_addr;
    s32 per_2_shp_addr;
    s32 mcu_2_shp_addr;
    s32 ata_2_mcu_addr;
    s32 mcu_2_ata_addr;
    s32 app_2_per_addr;
    s32 app_2_mcu_addr;
    s32 shp_2_per_addr;
    s32 shp_2_mcu_addr;
    s32 mshc_2_mcu_addr;
    s32 mcu_2_mshc_addr;
    s32 spdif_2_mcu_addr;
    s32 mcu_2_spdif_addr;
    s32 asrc_2_mcu_addr;
    s32 ext_mem_2_ipu_addr;
    s32 descrambler_addr;
    s32 dptc_dvfs_addr;
    s32 utra_addr;
    s32 ram_code_start_addr;
    s32 mcu_2_ssish_addr;
    s32 ssish_2_mcu_addr;
    s32 hdmi_dma_addr;

Re: imx6 SDMA and EIM bus

ao1 — Thu, 29 May 2014 15:15:24 GMT

Is it possble to get from freescale the source code of the ap_2_ap_fixed_ROM SDMA script?

Re: imx6 SDMA and EIM bus

christophecouta — Thu, 02 Jul 2015 11:18:10 GMT

Hi Andreas,

Did you get anywhere with your SDMA transfer from memory to FPGA? I have a similar case with a transfer from FPGA to memory that needs to be triggered from SDMA_EXT_EVENT0 and i could not figure out which ROM script is best to use in this case.

Regards,

Re: imx6 SDMA and EIM bus

Yuri — Wed, 05 Aug 2015 06:06:22 GMT

The SDMA ROM scripts do not use the SDMA_EXT_EVENT(s).
It is needed to design own scripts for it.

Regards,

Yuri.

Re: imx6 SDMA and EIM bus

Yuri — Wed, 05 Aug 2015 06:07:59 GMT

Sources codes of SDMA ROM scripts are not provided. Sorry.

Regards,

Yuri.

Re: imx6 SDMA and EIM bus

jial2012 — Mon, 30 Jul 2018 05:43:16 GMT

Hi,

I also have a similar case with a transfer from FPGA to memory that needs to be triggered from SDMA_EXT_EVENT0, did you solved your problem? please give me some information, I don't kown how to config the sdma and start the SDMA_EXT_EVENT0. Thank you very much!

Regards

Re: imx6 SDMA and EIM bus

rclongyunteng — Mon, 30 Jul 2018 08:11:53 GMT

Hi,

Recently i also try imx6 to use SDMA from EIM to DDR. What you mean is configure gpio17 to start SDMA_EXT_EVENT0?

I also have some questions.

How can i make imx6q work as external memory to internal memory please?

Any suggestion please? Thank you.

Best Regards

Re: imx6 SDMA and EIM bus

ao1 — Mon, 30 Jul 2018 08:35:59 GMT

Hello,

I think there was a problem with the version of the processor. SDMA_EXT _ EVENT0 never worked! Just SDMA_EXT_EVENT1 - Not sure if they have ever tested that. If your SoC is an old revision you might have that issue. Try on EXT_EVENT1. Which SDMA script are you going to use? Are you going to write one?

Kind regards,

Re: imx6 SDMA and EIM bus

jial2012 — Tue, 31 Jul 2018 01:03:32 GMT

Hi Andreas,

thank you for your reply. I just want to use SDMA_EXT _ EVENT0 to interrupt which triggled by an square wave input, when cpu received the dma interrupt, it go to the associate callback fuction to handle something. I don't need to copy data form fpga use sdma, I have another way to get fpga data to cpu memory, what i need is triggle the SDMA_EXT _ EVENT0 and go to the callback fuction.

I don't kown whether need to write a script, nor how to write one, its difficult for me. Also, I have not try the SDMA_EXT _ EVENT1 signal, because the pin not give out. Did you kown how I should do?

TIPS:

I have give a problem at the community of nxp https://community.nxp.com/message/1038802?commentID=1038802#comment-1038802 , the FAE's reply seems not clear to me.

Best Regards

ling jia

Re: imx6 SDMA and EIM bus

jial2012 — Tue, 31 Jul 2018 01:11:12 GMT

HI yunteng,

thank you for your reply. I just want to use SDMA_EXT _ EVENT0 to interrupt which triggled by an square wave input, when cpu received the dma interrupt, it go to the associate callback fuction to handle something. I don't need to copy data form fpga use sdma. I think you can use MEM_TO_MEM SDMA, there are many example in the nxp community, such as https://community.nxp.com/docs/DOC-103127 please search key words to get it.

Best Regards

Re: imx6 SDMA and EIM bus

rclongyunteng — Tue, 31 Jul 2018 03:35:13 GMT

Hi,

Thank you for your reply. It is useful.

Best Regards.